<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22990">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO table<br><br>As function platform_FchParams_reset() is no longer called or declared,<br>it needs to be removed. Replace GPIO table with the new format, and<br>platform_FchParams_reset() with new function board_get_gpio().<br><br>BUG=b:64140392<br>TEST=Build gardenia.<br><br>Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/amd/gardenia/Makefile.inc<br>M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>2 files changed, 28 insertions(+), 18 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/22990/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc</span><br><span>index 4c637bb..1825f42 100644</span><br><span>--- a/src/mainboard/amd/gardenia/Makefile.inc</span><br><span>+++ b/src/mainboard/amd/gardenia/Makefile.inc</span><br><span>@@ -19,6 +19,7 @@</span><br><span> romstage-y += BiosCallOuts.c</span><br><span> romstage-y += OemCustomize.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += bootblock/BiosCallOuts.c</span><br><span> ramstage-y += BiosCallOuts.c</span><br><span> ramstage-y += OemCustomize.c</span><br><span> ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c</span><br><span>diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c</span><br><span>index 7e60dae..30877a7 100644</span><br><span>--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c</span><br><span>+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c</span><br><span>@@ -18,33 +18,42 @@</span><br><span> #include <soc/southbridge.h></span><br><span> #include <stdlib.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const GPIO_CONTROL oem_gardenia_gpio[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The definitions bellow are valid only within this file, with the sole</span><br><span style="color: hsl(120, 100%, 40%);">+ * purpose of making the array below compact and easy to understand.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PULL_UP   FCH_GPIO_PULL_UP_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define PULL_DOWN      FCH_GPIO_PULL_DOWN_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INPUT                0</span><br><span style="color: hsl(120, 100%, 40%);">+#define OUTPUT_H     (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define OUTPUT_L      FCH_GPIO_OUTPUT_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * As a rule of thumb, GPIO used by coreboot should be initialized at</span><br><span style="color: hsl(120, 100%, 40%);">+ * STAGE_RESET while GPIO used only by the OS should be initialized at</span><br><span style="color: hsl(120, 100%, 40%);">+ * STAGE_INIT_LATE.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio gpio_set_stage[] = {</span><br><span>    /* BT radio disable */</span><br><span style="color: hsl(0, 100%, 40%);">-  {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE</span><br><span style="color: hsl(0, 100%, 40%);">-                                         | FCH_GPIO_OUTPUT_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+    {14, Function1, PULL_UP | OUTPUT_H, STAGE_INIT_LATE },</span><br><span>       /* NFC PU */</span><br><span style="color: hsl(0, 100%, 40%);">-    {64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE</span><br><span style="color: hsl(0, 100%, 40%);">-                                         | FCH_GPIO_OUTPUT_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+    {64, Function0, PULL_UP | OUTPUT_H, STAGE_RESET },</span><br><span>   /* NFC wake */</span><br><span style="color: hsl(0, 100%, 40%);">-  {65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE</span><br><span style="color: hsl(0, 100%, 40%);">-                                         | FCH_GPIO_OUTPUT_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+    {65, Function0, PULL_UP | OUTPUT_H, STAGE_INIT_LATE },</span><br><span>       /* Webcam */</span><br><span style="color: hsl(0, 100%, 40%);">-    {66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE</span><br><span style="color: hsl(0, 100%, 40%);">-                                         | FCH_GPIO_OUTPUT_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+    {66, Function0, PULL_UP | OUTPUT_H, STAGE_INIT_LATE },</span><br><span>       /* PCIe presence detect */</span><br><span style="color: hsl(0, 100%, 40%);">-      {69, Function0, FCH_GPIO_PULL_UP_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+     {69, Function0, PULL_UP | INPUT, STAGE_RESET },</span><br><span>      /* GPS sleep */</span><br><span style="color: hsl(0, 100%, 40%);">- {70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE</span><br><span style="color: hsl(0, 100%, 40%);">-                                         | FCH_GPIO_OUTPUT_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+    {70, Function0, PULL_UP | OUTPUT_H, STAGE_INIT_LATE },</span><br><span>       /* MUX for Power Express Eval */</span><br><span style="color: hsl(0, 100%, 40%);">-        {116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},</span><br><span style="color: hsl(120, 100%, 40%);">+  {116, Function1, PULL_DOWN | INPUT, STAGE_RESET },</span><br><span>   /* SD power */</span><br><span style="color: hsl(0, 100%, 40%);">-  {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE</span><br><span style="color: hsl(0, 100%, 40%);">-                                                 | FCH_GPIO_OUTPUT_ENABLE},</span><br><span style="color: hsl(0, 100%, 40%);">-     {-1}</span><br><span style="color: hsl(120, 100%, 40%);">+  {119, Function2, PULL_UP | OUTPUT_H, STAGE_RESET },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+    *size = ARRAY_SIZE(gpio_set_stage);</span><br><span style="color: hsl(120, 100%, 40%);">+   return  gpio_set_stage;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22990">change 22990</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22990"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd </div>
<div style="display:none"> Gerrit-Change-Number: 22990 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>