<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22982">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[UNTESTED]nb/intel/sandybridge: Use common mrc cache functions<br><br>This uses the functions in include/mrc_cache.h instead of<br>northbidge/intel/common/mrc_cache.h<br><br>Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/sandybridge/Kconfig<br>M src/northbridge/intel/sandybridge/Makefile.inc<br>M src/northbridge/intel/sandybridge/raminit.c<br>3 files changed, 12 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22982/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig</span><br><span>index 043e8de..a1f21a2 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/Kconfig</span><br><span>+++ b/src/northbridge/intel/sandybridge/Kconfig</span><br><span>@@ -16,7 +16,7 @@</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SANDYBRIDGE</span><br><span> bool</span><br><span style="color: hsl(0, 100%, 40%);">- select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_MRC_SETTINGS</span><br><span> select CPU_INTEL_MODEL_206AX</span><br><span> select HAVE_DEBUG_RAM_SETUP</span><br><span> select INTEL_GMA_ACPI</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_IVYBRIDGE</span><br><span> bool</span><br><span style="color: hsl(0, 100%, 40%);">- select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_MRC_SETTINGS</span><br><span> select CPU_INTEL_MODEL_306AX</span><br><span> select HAVE_DEBUG_RAM_SETUP</span><br><span> select INTEL_GMA_ACPI</span><br><span>diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>index 846d31b..1470353 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>@@ -45,16 +45,4 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifneq ($(CONFIG_CHROMEOS),y)</span><br><span style="color: hsl(0, 100%, 40%);">-$(obj)/mrc.cache: $(obj)/config.h</span><br><span style="color: hsl(0, 100%, 40%);">- dd if=/dev/zero count=1 \</span><br><span style="color: hsl(0, 100%, 40%);">- bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \</span><br><span style="color: hsl(0, 100%, 40%);">- tr '\000' '\377' > $@</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cbfs-files-y += mrc.cache</span><br><span style="color: hsl(0, 100%, 40%);">-mrc.cache-file := $(obj)/mrc.cache</span><br><span style="color: hsl(0, 100%, 40%);">-mrc.cache-align := 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">-mrc.cache-type := mrc_cache</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>index 12384b4..4ec1adf 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #include <cbmem.h></span><br><span> #include <halt.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/intel/common/mrc_cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <mrc_cache.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include <cpu/x86/msr.h></span><br><span>@@ -35,6 +35,8 @@</span><br><span> #include "raminit_common.h"</span><br><span> #include "sandybridge.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_CACHE_VERSION 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* FIXME: no ECC support. */</span><br><span> /* FIXME: no support for 3-channel chipsets. */</span><br><span> </span><br><span>@@ -292,7 +294,8 @@</span><br><span> static void save_timings(ramctr_timing *ctrl)</span><br><span> {</span><br><span> /* Save the MRC S3 restore data to cbmem */</span><br><span style="color: hsl(0, 100%, 40%);">- store_current_mrc_cache(ctrl, sizeof(*ctrl));</span><br><span style="color: hsl(120, 100%, 40%);">+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(*ctrl));</span><br><span> }</span><br><span> </span><br><span> static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,</span><br><span>@@ -311,7 +314,7 @@</span><br><span> ramctr_timing ctrl;</span><br><span> int fast_boot;</span><br><span> spd_raw_data spds[4];</span><br><span style="color: hsl(0, 100%, 40%);">- struct mrc_data_container *mrc_cache;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct region_device rdev;</span><br><span> ramctr_timing *ctrl_cached;</span><br><span> struct cpuid_result cpures;</span><br><span> int err;</span><br><span>@@ -347,8 +350,9 @@</span><br><span> early_thermal_init();</span><br><span> </span><br><span> /* try to find timings in MRC cache */</span><br><span style="color: hsl(0, 100%, 40%);">- mrc_cache = find_current_mrc_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,</span><br><span style="color: hsl(120, 100%, 40%);">+ &rdev);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) {</span><br><span> if (s3resume) {</span><br><span> /* Failed S3 resume, reset to come up cleanly */</span><br><span> outb(0x6, 0xcf9);</span><br><span>@@ -356,7 +360,7 @@</span><br><span> }</span><br><span> ctrl_cached = NULL;</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl_cached = rdev_mmap_full(&rdev);</span><br><span> }</span><br><span> </span><br><span> /* verify MRC cache for fast boot */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22982">change 22982</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22982"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 </div>
<div style="display:none"> Gerrit-Change-Number: 22982 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>