<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22980">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801ix: Use the common ACPI pirq generator<br><br>For this to work the northbridge and lpc bridge device need acpi_name<br>functions.<br><br>This also needs DEFAULT_RCBA being configured in Kconfig.<br><br>Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>D src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl<br>D src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl<br>D src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl<br>M src/northbridge/intel/gm45/acpi/hostbridge.asl<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/southbridge/intel/i82801ix/Kconfig<br>M src/southbridge/intel/i82801ix/i82801ix.h<br>M src/southbridge/intel/i82801ix/lpc.c<br>8 files changed, 32 insertions(+), 245 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/22980/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl</span><br><span>deleted file mode 100644</span><br><span>index aefdf94..0000000</span><br><span>--- a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,80 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is board specific information: IRQ routing for the</span><br><span style="color: hsl(0, 100%, 40%);">- * gm45</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI Interrupt Routing</span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- If (PICM) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Graphics 0:1.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0001ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard GbE</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0019ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1a.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1d.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC bridge sub devices 0:1f.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, 0, 18 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Graphics 0:1.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard GbE</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1a.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1d.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC bridge sub devices 0:1f.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl</span><br><span>deleted file mode 100644</span><br><span>index aefdf94..0000000</span><br><span>--- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,80 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is board specific information: IRQ routing for the</span><br><span style="color: hsl(0, 100%, 40%);">- * gm45</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI Interrupt Routing</span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- If (PICM) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Graphics 0:1.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0001ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard GbE</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0019ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1a.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1d.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC bridge sub devices 0:1f.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, 0, 18 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Graphics 0:1.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard GbE</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1a.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1d.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC bridge sub devices 0:1f.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl</span><br><span>deleted file mode 100644</span><br><span>index 4a9ede8..0000000</span><br><span>--- a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,80 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is board specific information: IRQ routing for the</span><br><span style="color: hsl(0, 100%, 40%);">- * gm45</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI Interrupt Routing</span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- If (PICM) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Graphics 0:1.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0001ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1a.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1d.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // FIXME</span><br><span style="color: hsl(0, 100%, 40%);">- // CardBus/IEEE1394 0:1e.2, 0:1e.3</span><br><span style="color: hsl(0, 100%, 40%);">- // Package() { 0x001effff, 0, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Package() { 0x001effff, 1, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC device 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, 0, 18 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Graphics 0:1.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1a.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // USB and EHCI 0:1d.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // FIXME</span><br><span style="color: hsl(0, 100%, 40%);">- // CardBus/IEEE1394 0:1e.2, 0:1e.3</span><br><span style="color: hsl(0, 100%, 40%);">- // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC device 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl</span><br><span>index c674df5..afa7a61 100644</span><br><span>--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl</span><br><span>+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl</span><br><span>@@ -228,6 +228,3 @@</span><br><span> </span><br><span> Return (MCRS)</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "acpi/gm45_pci_irqs.asl"</span><br><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index 8215979..431d98d 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -186,6 +186,22 @@</span><br><span> pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const char *northbridge_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PCI0";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.pci.devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(0, 0):</span><br><span style="color: hsl(120, 100%, 40%);">+ return "MCHC";</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static struct device_operations pci_domain_ops = {</span><br><span> .read_resources = mch_domain_read_resources,</span><br><span> .set_resources = mch_domain_set_resources,</span><br><span>@@ -195,6 +211,7 @@</span><br><span> .ops_pci_bus = pci_bus_default_ops,</span><br><span> .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = northbridge_acpi_name,</span><br><span> };</span><br><span> </span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig</span><br><span>index 6879bce..2752e7a 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/Kconfig</span><br><span>+++ b/src/southbridge/intel/i82801ix/Kconfig</span><br><span>@@ -18,6 +18,7 @@</span><br><span> bool</span><br><span> select SOUTHBRIDGE_INTEL_COMMON</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ</span><br><span> select IOAPIC</span><br><span> select HAVE_USBDEBUG</span><br><span> select HAVE_HARD_RESET</span><br><span>@@ -33,6 +34,10 @@</span><br><span> hex</span><br><span> default 0xfef00000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DEFAULT_RCBA</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config HPET_MIN_TICKS</span><br><span> hex</span><br><span> default 0x80</span><br><span>diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>index 38dfa38..90e8953 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>+++ b/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>@@ -26,9 +26,9 @@</span><br><span> </span><br><span> #define DEFAULT_TBAR ((u8 *)0xfed1b000)</span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA ((u8 *)CONFIG_DEFAULT_RCBA)</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA CONFIG_DEFAULT_RCBA</span><br><span> #endif</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)</span><br><span>diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c</span><br><span>index bc45b9d..dc582c9 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/lpc.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/lpc.c</span><br><span>@@ -34,6 +34,7 @@</span><br><span> #include "nvs.h"</span><br><span> #include <southbridge/intel/common/pciehp.h></span><br><span> #include <drivers/intel/gma/i915.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/acpi_pirq_gen.h></span><br><span> </span><br><span> #define NMI_OFF 0</span><br><span> </span><br><span>@@ -558,12 +559,18 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const char *lpc_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return "LPCB";</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void southbridge_fill_ssdt(device_t device)</span><br><span> {</span><br><span> device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> config_t *chip = dev->chip_info;</span><br><span> </span><br><span> intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_acpi_gen_def_acpi_pirq(device);</span><br><span> }</span><br><span> </span><br><span> static struct pci_operations pci_ops = {</span><br><span>@@ -577,6 +584,7 @@</span><br><span> .acpi_inject_dsdt_generator = southbridge_inject_dsdt,</span><br><span> .write_acpi_tables = acpi_write_hpet,</span><br><span> .acpi_fill_ssdt_generator = southbridge_fill_ssdt,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = lpc_acpi_name,</span><br><span> .init = lpc_init,</span><br><span> .scan_bus = scan_lpc_bus,</span><br><span> .ops_pci = &pci_ops,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22980">change 22980</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22980"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 </div>
<div style="display:none"> Gerrit-Change-Number: 22980 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>