<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22954">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL<br><br>Even though kaby lake and cannon lake are using the same GSPI<br>controller, bit meanings (for polarity and state) in SPI_CS_CONTROL<br>register are significantly different. This change provides and uses<br>SoC-specific callbacks to identify the right bits to be used for<br>polarity and state while programming the SPI_CS_CONTROL register.<br><br>BUG=b:70628116<br><br>Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/soc/intel/cannonlake/gspi.c<br>M src/soc/intel/common/block/gspi/gspi.c<br>M src/soc/intel/common/block/include/intelblocks/gspi.h<br>M src/soc/intel/skylake/gspi.c<br>4 files changed, 91 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22954/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c</span><br><span>index e4f682d..9755ac9 100644</span><br><span>--- a/src/soc/intel/cannonlake/gspi.c</span><br><span>+++ b/src/soc/intel/cannonlake/gspi.c</span><br><span>@@ -44,6 +44,30 @@</span><br><span> return EARLY_GSPI_BASE_ADDRESS;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Polarity field in SPI_CS_CONTROL indicates inactive polarity. */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_INACTIVE_POLARITY_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_INACTIVE_POLARITY_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t gspi_soc_csctrl_polarity(unsigned int gspi_bus, enum spi_polarity pol)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pol == SPI_POLARITY_LOW)</span><br><span style="color: hsl(120, 100%, 40%);">+ return CS_INACTIVE_POLARITY_HIGH;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return CS_INACTIVE_POLARITY_LOW;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t gspi_soc_csctrl_state(unsigned int gspi_bus, uint32_t cs_ctrl_pol,</span><br><span style="color: hsl(120, 100%, 40%);">+ enum cs_assert cs_assert)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * CS_STATE field in SPI_CS_CONTROL register indicates</span><br><span style="color: hsl(120, 100%, 40%);">+ * assert/de-assert.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ return cs_assert;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust</span><br><span> * the bus # accordingly when referring to SPI / GSPI bus numbers.</span><br><span>diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c</span><br><span>index 8e527ed..d6b303d 100644</span><br><span>--- a/src/soc/intel/common/block/gspi/gspi.c</span><br><span>+++ b/src/soc/intel/common/block/gspi/gspi.c</span><br><span>@@ -92,12 +92,11 @@</span><br><span> #define SSP_REG 0x220 /* SSP Reg */</span><br><span> #define DMA_FINISH_DISABLE (1 << 0)</span><br><span> #define SPI_CS_CONTROL 0x224 /* SPI CS Control */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS_POLARITY_LOW (0 << 12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS_POLARITY_HIGH (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CS_0_POL_SHIFT (12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CS_0_POL_MASK (1 << CS_0_POL_SHIFT)</span><br><span> #define CS_0 (0 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS_STATE_LOW (0 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS_STATE_HIGH (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS_STATE_MASK (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CS_STATE_SHIFT (1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CS_STATE_MASK (1 << CS_STATE_SHIFT)</span><br><span> #define CS_MODE_HW (0 << 0)</span><br><span> #define CS_MODE_SW (1 << 0)</span><br><span> </span><br><span>@@ -260,25 +259,18 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-enum cs_assert {</span><br><span style="color: hsl(0, 100%, 40%);">- CS_ASSERT,</span><br><span style="color: hsl(0, 100%, 40%);">- CS_DEASSERT,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void __gspi_cs_change(const struct gspi_ctrlr_params *p,</span><br><span> enum cs_assert cs_assert)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t cs_ctrl, state;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cs_ctrl, pol;</span><br><span> cs_ctrl = gspi_read_mmio_reg(p, SPI_CS_CONTROL);</span><br><span> </span><br><span> cs_ctrl &= ~CS_STATE_MASK;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (cs_ctrl & CS_POLARITY_HIGH)</span><br><span style="color: hsl(0, 100%, 40%);">- state = (cs_assert == CS_ASSERT) ? CS_STATE_HIGH : CS_STATE_LOW;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- state = (cs_assert == CS_ASSERT) ? CS_STATE_LOW : CS_STATE_HIGH;</span><br><span style="color: hsl(120, 100%, 40%);">+ pol = !!(cs_ctrl & CS_0_POL_MASK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- cs_ctrl |= state;</span><br><span style="color: hsl(120, 100%, 40%);">+ cs_ctrl |= !!gspi_soc_csctrl_state(p->gspi_bus, pol,</span><br><span style="color: hsl(120, 100%, 40%);">+ cs_assert) << CS_STATE_SHIFT;</span><br><span> </span><br><span> gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);</span><br><span> }</span><br><span>@@ -330,7 +322,7 @@</span><br><span> static int gspi_ctrlr_setup(const struct spi_slave *dev)</span><br><span> {</span><br><span> struct spi_cfg cfg;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;</span><br><span> struct gspi_ctrlr_params params, *p = ¶ms;</span><br><span> </span><br><span> /* Only chip select 0 is supported. */</span><br><span>@@ -364,10 +356,10 @@</span><br><span> * - Do not assert CS.</span><br><span> */</span><br><span> cs_ctrl = CS_MODE_SW | CS_0;</span><br><span style="color: hsl(0, 100%, 40%);">- if (cfg.cs_polarity == SPI_POLARITY_LOW)</span><br><span style="color: hsl(0, 100%, 40%);">- cs_ctrl |= CS_POLARITY_LOW | CS_STATE_HIGH;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- cs_ctrl |= CS_POLARITY_HIGH | CS_STATE_LOW;</span><br><span style="color: hsl(120, 100%, 40%);">+ pol = !!gspi_soc_csctrl_polarity(p->gspi_bus, cfg.cs_polarity);</span><br><span style="color: hsl(120, 100%, 40%);">+ cs_ctrl |= pol << CS_0_POL_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ cs_ctrl |= !!gspi_soc_csctrl_state(p->gspi_bus, pol,</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_DEASSERT) << CS_STATE_SHIFT;</span><br><span> gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);</span><br><span> </span><br><span> /* Disable SPI controller. */</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/gspi.h b/src/soc/intel/common/block/include/intelblocks/gspi.h</span><br><span>index 4e10e25..4b0f3cc 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/gspi.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/gspi.h</span><br><span>@@ -29,6 +29,11 @@</span><br><span> uint8_t early_init;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+enum cs_assert {</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_ASSERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_DEASSERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* GSPI controller APIs. */</span><br><span> void gspi_early_bar_init(void);</span><br><span> </span><br><span>@@ -65,4 +70,21 @@</span><br><span> */</span><br><span> int gspi_get_soc_spi_cfg(unsigned int bus, struct spi_cfg *cfg);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SoC callback to return the value of CS_0_POLARITY field in SPI_CS_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+ * register based on the following input parameters:</span><br><span style="color: hsl(120, 100%, 40%);">+ * gspi_bus = GSPI bus number</span><br><span style="color: hsl(120, 100%, 40%);">+ * pol = Active polarity of chip-select to the SPI device</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t gspi_soc_csctrl_polarity(unsigned int gspi_bus, enum spi_polarity pol);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SoC callback to return the value of CS_STATE field in SPI_CS_CONTROL register</span><br><span style="color: hsl(120, 100%, 40%);">+ * based on the following input parameters:</span><br><span style="color: hsl(120, 100%, 40%);">+ * gspi_bus = GSPI bus number</span><br><span style="color: hsl(120, 100%, 40%);">+ * cs_ctrl_pol = Value of polarity field in SPI_CS_CONTROL register</span><br><span style="color: hsl(120, 100%, 40%);">+ * cs_assert = Chip-select operation to be performed(assert/de-assert)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t gspi_soc_csctrl_state(unsigned int gspi_bus, uint32_t cs_ctrl_pol,</span><br><span style="color: hsl(120, 100%, 40%);">+ enum cs_assert cs_assert);</span><br><span> #endif /* SOC_INTEL_COMMON_BLOCK_GSPI_H */</span><br><span>diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c</span><br><span>index 252be77..910f59f 100644</span><br><span>--- a/src/soc/intel/skylake/gspi.c</span><br><span>+++ b/src/soc/intel/skylake/gspi.c</span><br><span>@@ -43,6 +43,38 @@</span><br><span> return EARLY_GSPI_BASE_ADDRESS;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Polarity field in SPI_CS_CONTROL indicates active polarity. */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_ACTIVE_POLARITY_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_ACTIVE_POLARITY_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_STATE_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_STATE_HIGH</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t gspi_soc_csctrl_polarity(unsigned int gspi_bus, enum spi_polarity pol)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pol == SPI_POLARITY_LOW)</span><br><span style="color: hsl(120, 100%, 40%);">+ return CS_ACTIVE_POLARITY_LOW;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return CS_ACTIVE_POLARITY_HIGH;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t gspi_soc_csctrl_state(unsigned int gspi_bus, uint32_t cs_ctrl_pol,</span><br><span style="color: hsl(120, 100%, 40%);">+ enum cs_assert cs_assert)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t state;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cs_ctrl_pol == CS_ACTIVE_POLARITY_HIGH)</span><br><span style="color: hsl(120, 100%, 40%);">+ state = (cs_assert == CS_ASSERT) ? CS_STATE_HIGH : CS_STATE_LOW;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ state = (cs_assert == CS_ASSERT) ? CS_STATE_LOW : CS_STATE_HIGH;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return state;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust</span><br><span> * the bus # accordingly when referring to SPI / GSPI bus numbers.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22954">change 22954</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22954"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 </div>
<div style="display:none"> Gerrit-Change-Number: 22954 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>