<p>JianfengX Zhou has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22943">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">libpayload/arch/x86: support read cpu speed from msr<br><br>on icelake, "while (!(inb(0x61) & 0x20))" lead to dead loop,<br>can not boot normally.<br><br>when CONFIG_LP_GET_CPU_SPEED_FROM_MSR set to 1, read cpu speed from<br>msr platfrom information register.<br><br>Change-Id: I69da73ab479785c7b5d8add15705c1cd42925a75<br>Signed-off-by: zhouji3x <jianfengx.zhou@intel.com><br>---<br>M payloads/libpayload/arch/x86/timer.c<br>1 file changed, 16 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22943/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c</span><br><span>index bf0c30a..845876f 100644</span><br><span>--- a/payloads/libpayload/arch/x86/timer.c</span><br><span>+++ b/payloads/libpayload/arch/x86/timer.c</span><br><span>@@ -46,6 +46,21 @@</span><br><span>  *</span><br><span>  * @return The CPU speed in kHz.</span><br><span>  */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef CONFIG_LP_GET_CPU_SPEED_FROM_MSR</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned int get_cpu_speed(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+        uint32_t info_lo;</span><br><span style="color: hsl(120, 100%, 40%);">+     uint32_t info_hi;</span><br><span style="color: hsl(120, 100%, 40%);">+     unsigned max_nb_ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      /* read MSR PLATFORM INFO */</span><br><span style="color: hsl(120, 100%, 40%);">+  asm volatile ("rdmsr" : "=a" (info_lo), "=d" (info_hi) : "c" (0xce));</span><br><span style="color: hsl(120, 100%, 40%);">+ max_nb_ratio = (info_lo >> 8) & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     cpu_khz = 100 * max_nb_ratio * 1000;</span><br><span style="color: hsl(120, 100%, 40%);">+  return cpu_khz;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> unsigned int get_cpu_speed(void)</span><br><span> {</span><br><span>   unsigned long long start, end;</span><br><span>@@ -76,3 +91,4 @@</span><br><span> </span><br><span>       return cpu_khz;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22943">change 22943</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22943"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I69da73ab479785c7b5d8add15705c1cd42925a75 </div>
<div style="display:none"> Gerrit-Change-Number: 22943 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: JianfengX Zhou <jianfengx.zhou@intel.com> </div>