<p>Renze Nicolai has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22922">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/ms7721: Fix HWM/Superio settings<br><br>This patch allows the temperature sensors to function.<br><br>Change-Id: I6491171eacc0c9848ba86ba7a62ec440226aae36<br>Signed-off-by: Renze Nicolai <renze@rnplus.nl><br>---<br>M src/mainboard/msi/ms7721/devicetree.cb<br>M src/superio/fintek/f71869ad/chip.h<br>M src/superio/fintek/f71869ad/f71869ad_hwm.c<br>3 files changed, 19 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/22922/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb</span><br><span>index d46eb84..9b76149 100644</span><br><span>--- a/src/mainboard/msi/ms7721/devicetree.cb</span><br><span>+++ b/src/mainboard/msi/ms7721/devicetree.cb</span><br><span>@@ -68,14 +68,16 @@</span><br><span>                                            # HWM configuration registers</span><br><span>                                                register "hwm_smbus_address" = "0x98"</span><br><span>                                            register "hwm_smbus_control_reg" = "0x02"</span><br><span style="color: hsl(0, 100%, 40%);">-                                           register "hwm_fan_type_sel_reg" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+                                          register "hwm_fan_type_sel_reg" = "0x10"</span><br><span>                                                 register "hwm_fan1_temp_adj_rate_reg" = "0x33"</span><br><span style="color: hsl(0, 100%, 40%);">-                                              register "hwm_fan_mode_sel_reg" = "0x07"</span><br><span style="color: hsl(120, 100%, 40%);">+                                          register "hwm_fan_mode_sel_reg" = "0x15"</span><br><span>                                                 register "hwm_fan1_idx_rpm_mode" = "0x0e"</span><br><span>                                                register "hwm_fan1_seg1_speed_count" = "0xff"</span><br><span>                                            register "hwm_fan1_seg2_speed_count" = "0x0e"</span><br><span>                                            register "hwm_fan1_seg3_speed_count" = "0x07"</span><br><span>                                            register "hwm_fan1_temp_map_sel" = "0x8c"</span><br><span style="color: hsl(120, 100%, 40%);">+                                         register "hwm_temp_sensor_type" = "0x08"</span><br><span style="color: hsl(120, 100%, 40%);">+                                          </span><br><span>                                             device pnp 4e.00 off end</span><br><span>                                             device pnp 4e.01 on     # COM1</span><br><span>                                                       io 0x60 = 0x3f8</span><br><span>@@ -92,7 +94,7 @@</span><br><span>                                                  irq 0xf0 = 0x44 # PRT Mode Select Register</span><br><span>                                           end</span><br><span>                                          device pnp 4e.04 on     # Hardware Monitor</span><br><span style="color: hsl(0, 100%, 40%);">-                                                      io 0x60 = 0x600</span><br><span style="color: hsl(120, 100%, 40%);">+                                                       io 0x60 = 0x225</span><br><span>                                                      irq 0x70 = 0</span><br><span>                                                 end</span><br><span>                                          device pnp 4e.05 on     # KBC</span><br><span>@@ -141,9 +143,16 @@</span><br><span>                                                         #irq 0x83 = 0x00        # GPIO7 drive enable</span><br><span>                                                 end</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-                                         device pnp 4e.07 on end # WDT</span><br><span style="color: hsl(0, 100%, 40%);">-                                           device pnp 4e.08 off end        # CIR</span><br><span style="color: hsl(0, 100%, 40%);">-                                           device pnp 4e.0a on end # PME</span><br><span style="color: hsl(120, 100%, 40%);">+                                         device pnp 4e.07 on end       # WDT</span><br><span style="color: hsl(120, 100%, 40%);">+                                           device pnp 4e.08 off end      # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+                                           device pnp 4e.0a on         # PME</span><br><span style="color: hsl(120, 100%, 40%);">+                                               irq 0xe0 = 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+                                               irq 0xe1 = 0xc0</span><br><span style="color: hsl(120, 100%, 40%);">+                                               irq 0xe2 = 0x0c</span><br><span style="color: hsl(120, 100%, 40%);">+                                               irq 0xe8 = 0x00 #Wakeup Enable [RI2, -, RI1, RING, GP, TIMEOUT, MOUSE, KB]</span><br><span style="color: hsl(120, 100%, 40%);">+                                            irq 0xf8 = 0x1c #Led VCC Mode Select</span><br><span style="color: hsl(120, 100%, 40%);">+                                                  irq 0xf9 = 0x15 #Led VSB Mode Select</span><br><span style="color: hsl(120, 100%, 40%);">+                                                end</span><br><span>                                  end # f71869ad</span><br><span>                               end     #device pci 14.3 # LPC</span><br><span>                               device pci 14.4 on  end # PCI 0x4384 (PCI slot on board)</span><br><span>diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h</span><br><span>index 4e4323e..7424e9a 100644</span><br><span>--- a/src/superio/fintek/f71869ad/chip.h</span><br><span>+++ b/src/superio/fintek/f71869ad/chip.h</span><br><span>@@ -37,6 +37,7 @@</span><br><span>    uint8_t hwm_fan1_seg2_speed_count;</span><br><span>   uint8_t hwm_fan1_seg3_speed_count;</span><br><span>   uint8_t hwm_fan1_temp_map_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+    uint8_t hwm_temp_sensor_type;</span><br><span> };</span><br><span> </span><br><span> #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */</span><br><span>diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c</span><br><span>index d253e5f..e7d6483 100644</span><br><span>--- a/src/superio/fintek/f71869ad/f71869ad_hwm.c</span><br><span>+++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c</span><br><span>@@ -50,6 +50,7 @@</span><br><span> #define HWM_FAN1_SEG2_SPEED_COUNT  0xAB</span><br><span> #define HWM_FAN1_SEG3_SPEED_COUNT  0xAC</span><br><span> #define HWM_FAN1_TEMP_MAP_SEL      0xAF</span><br><span style="color: hsl(120, 100%, 40%);">+#define HWM_TEMP_SENSOR_TYPE       0x6B</span><br><span> </span><br><span> /* note: multifunc registers need to be tweaked before here */</span><br><span> void f71869ad_hwm_init(struct device *dev)</span><br><span>@@ -97,6 +98,8 @@</span><br><span>        pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count);</span><br><span>        pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count);</span><br><span>        pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count);</span><br><span style="color: hsl(120, 100%, 40%);">+    /* Temperature sensor type */</span><br><span style="color: hsl(120, 100%, 40%);">+    pnp_write_index(port, HWM_TEMP_SENSOR_TYPE, conf->hwm_temp_sensor_type);</span><br><span> </span><br><span>        pnp_exit_conf_mode(dev);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22922">change 22922</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22922"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6491171eacc0c9848ba86ba7a62ec440226aae36 </div>
<div style="display:none"> Gerrit-Change-Number: 22922 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Renze Nicolai <renze@rnplus.nl> </div>