<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22940">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/kahlee: Create mainboard_pirq_data<br><br>When booting kahlee, there's an error message: "Warning: Can't write PCI<br>IRQ assignments because 'mainboard_pirq_data' structure does not exist".<br>This is caused by missing mainboard_pirq_data.<br><br>Create mainboard_pirq_data and update pirq_setup() to set the values of<br>pirq_data_ptr and pirq_data_size.<br><br>BUG=b:70788755<br>TEST=Build and boot kahlee. Warning message must be gone. Verify output<br>from write_pci_cfg_irqs and explain anything that does not fit a pattern<br>(what all other devices are producing).<br><br>Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/google/kahlee/mainboard.c<br>1 file changed, 28 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22940/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c</span><br><span>index 0954a29..6deac3f 100644</span><br><span>--- a/src/mainboard/google/kahlee/mainboard.c</span><br><span>+++ b/src/mainboard/google/kahlee/mainboard.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <baseboard/variants.h></span><br><span> #include <boardid.h></span><br><span> #include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span> #include <soc/smi.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <variant/ec.h></span><br><span>@@ -77,9 +78,36 @@</span><br><span> [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This table defines the index into the picr/intr_data</span><br><span style="color: hsl(120, 100%, 40%);">+ * tables for each device. Any enabled device and slot</span><br><span style="color: hsl(120, 100%, 40%);">+ * that uses hardware interrupts should have an entry</span><br><span style="color: hsl(120, 100%, 40%);">+ * in this table to define its index into the FCH</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCI_INTR register 0xC00/0xC01. This index will define</span><br><span style="color: hsl(120, 100%, 40%);">+ * the interrupt that it should use. Putting PIRQ_A into</span><br><span style="color: hsl(120, 100%, 40%);">+ * the PIN A index for a device will tell that device to</span><br><span style="color: hsl(120, 100%, 40%);">+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pirq_struct mainboard_pirq_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE0_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {HDA0_DEVFN, {PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC} }, /* HDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SMBUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ {EHCI1_DEVFN, {PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* EHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ {XHCI_DEVFN, {PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* XHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* PIRQ Setup */</span><br><span> static void pirq_setup(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_data_ptr = mainboard_pirq_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);</span><br><span> intr_data_ptr = mainboard_intr_data;</span><br><span> picr_data_ptr = mainboard_picr_data;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22940">change 22940</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a </div>
<div style="display:none"> Gerrit-Change-Number: 22940 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>