<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22876">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Force PSP command reg settings in bootblock<br><br>A subsequent patch to the PSP library will rely on the device already<br>having its PCI command register set to allow memory decoding and<br>mastering enabled.<br><br>Program the command register ahead of loading the SMU FW1 blob in<br>bootblock.  When the device has not been set up (e.g. when SMU FW<br>is not selectable), AGESA sets up the device.  As a result, a<br>similar change is not required before sending the DRAM ready<br>command.<br><br>Change-Id: Id586106751286c4767b5c16ed7e1604523635492<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>1 file changed, 6 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22876/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>index 030c990..9f3827d 100644<br>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>@@ -88,7 +88,7 @@<br>  */<br> static void load_smu_fw1(void)<br> {<br>- u32 base, limit;<br>+     u32 base, limit, cmd;<br> <br>      /* Open a posted hole from 0x80000000 : 0xfed00000-1 */<br>       base =  0x80000000;<br>@@ -101,6 +101,11 @@<br>     pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);<br>      pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);<br> <br>+     /* Enable memory access and master */<br>+        cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);<br>+   cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;<br>+      pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);<br>+<br>         psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22876">change 22876</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22876"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id586106751286c4767b5c16ed7e1604523635492 </div>
<div style="display:none"> Gerrit-Change-Number: 22876 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>