<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22869">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Add missing SoC common function into SMM library<br><br>Modify SMM common code in order to accommodate Skylake SOC code.<br><br>Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/smihandler.h<br>M src/soc/intel/common/block/include/intelblocks/smm.h<br>M src/soc/intel/common/block/smm/smihandler.c<br>M src/soc/intel/common/block/smm/smm.c<br>4 files changed, 45 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22869/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h<br>index 5df5552..cab8a1e 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h<br>@@ -60,6 +60,11 @@<br> */<br> extern const smi_handler_t southbridge_smi[32];<br> <br>+#define SMI_HANDLER_SCI_EN(__bit) (1 << (__bit))<br>+<br>+/* SMI handlers that should be serviced in SCI mode too. */<br>+extern uint32_t smi_handler_sci_mask;<br>+<br> /*<br> * This function should be implemented in SOC specific code to handle<br> * the SMI event on SLP_EN. The default functionality is provided in<br>@@ -145,6 +150,12 @@<br> int smihandler_disable_busmaster(device_t dev);<br> <br> /*<br>+ * SoC needs to implement the mechanism to know if an illegal attempt<br>+ * has been made to write to the BIOS area.<br>+ */<br>+void smihandler_check_illegal_access(uint32_t tco_sts);<br>+<br>+/*<br> * Returns gnvs pointer within SMM context<br> */<br> struct global_nvs_t *smm_get_gnvs(void);<br>diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h<br>index 84f34a5..54f9005 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/smm.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/smm.h<br>@@ -29,7 +29,7 @@<br> * SMIs.<br> */<br> void smm_southbridge_clear_state(void);<br>-void smm_southbridge_enable(void);<br>+void smm_southbridge_enable(uint16_t events);<br> /* API to get SMM region start and size based on Host Bridge register */<br> void smm_region_info(void **start, size_t *size);<br> <br>diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c<br>index 7821dba..c01ed4f 100644<br>--- a/src/soc/intel/common/block/smm/smihandler.c<br>+++ b/src/soc/intel/common/block/smm/smihandler.c<br>@@ -21,6 +21,7 @@<br> #include <cpu/x86/smm.h><br> #include <device/pci_def.h><br> #include <elog.h><br>+#include <intelblocks/fast_spi.h><br> #include <intelblocks/pmclib.h><br> #include <intelblocks/smihandler.h><br> #include <intelblocks/uart.h><br>@@ -38,6 +39,15 @@<br> __attribute__((weak)) int smihandler_disable_busmaster(device_t dev)<br> {<br> return 1;<br>+}<br>+<br>+/*<br>+ * SoC needs to implement the mechanism to know if an illegal attempt<br>+ * has been made to write to the BIOS area.<br>+ */<br>+__attribute__((weak)) void smihandler_check_illegal_access(uint32_t tco_sts)<br>+{<br>+ return;<br> }<br> <br> static void *find_save_state(const struct smm_save_state_ops *save_state_ops,<br>@@ -175,6 +185,8 @@<br> <br> /* Disable all GPE */<br> pmc_disable_all_gpe();<br>+ /* Set which state system will be after power reapplied */<br>+ pmc_soc_restore_power_failure();<br> /* also iterates over all bridges on bus 0 */<br> busmaster_disable_on_bus(0);<br> break;<br>@@ -201,8 +213,7 @@<br> * the line above. However, if we entered sleep state S1 and wake<br> * up again, we will continue to execute code in this function.<br> */<br>- reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br>- if (reg32 & SCI_EN) {<br>+ if (pmc_read_pm1_control() & SCI_EN) {<br> /* The OS is not an ACPI OS, so we set the state to S0 */<br> pmc_disable_pm1_control(SLP_EN | SLP_TYP);<br> }<br>@@ -240,6 +251,9 @@<br> }<br> finalize_done = 1;<br> <br>+ if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))<br>+ /* Re-init SPI driver to handle locked BAR */<br>+ fast_spi_init();<br> }<br> <br> void smihandler_southbridge_apmc(<br>@@ -308,12 +322,13 @@<br> const struct smm_save_state_ops *save_state_ops)<br> {<br> uint16_t pm1_sts = pmc_clear_pm1_status();<br>+ u16 pm1_en = pmc_read_pm1_enable();<br> <br> /*<br> * While OSPM is not active, poweroff immediately<br> * on a power button event.<br> */<br>- if (pm1_sts & PWRBTN_STS) {<br>+ if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) {<br> /* power button pressed */<br> if (IS_ENABLED(CONFIG_ELOG_GSMI))<br> elog_add_event(ELOG_TYPE_POWER_BUTTON);<br>@@ -336,6 +351,8 @@<br> /* Any TCO event? */<br> if (!tco_sts)<br> return;<br>+<br>+ smihandler_check_illegal_access(tco_sts);<br> <br> if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */<br> /* Handle TCO timeout */<br>@@ -391,6 +408,17 @@<br> */<br> smi_sts = pmc_clear_smi_status();<br> <br>+ /*<br>+ * In SCI mode, execute only those SMI handlers that have<br>+ * declared themselves as available for service in that mode<br>+ * using smi_handler_sci_mask.<br>+ */<br>+ if (pmc_read_pm1_control() & SCI_EN)<br>+ smi_sts &= smi_handler_sci_mask;<br>+<br>+ if (!smi_sts)<br>+ return;<br>+<br> save_state_ops = get_smm_save_state_ops();<br> <br> /* Call SMI sub handler for each of the status bits */<br>diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c<br>index d5f42a7..feb6ad0 100644<br>--- a/src/soc/intel/common/block/smm/smm.c<br>+++ b/src/soc/intel/common/block/smm/smm.c<br>@@ -38,11 +38,11 @@<br> pmc_clear_all_gpe_status();<br> }<br> <br>-void smm_southbridge_enable(void)<br>+void smm_southbridge_enable(uint16_t events)<br> {<br> printk(BIOS_DEBUG, "Enabling SMIs.\n");<br> /* Configure events */<br>- pmc_enable_pm1(PWRBTN_EN | GBL_EN);<br>+ pmc_enable_pm1(events);<br> pmc_disable_std_gpe(PME_B0_EN);<br> <br> /*<br></pre><p>To view, visit <a href="https://review.coreboot.org/22869">change 22869</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2 </div>
<div style="display:none"> Gerrit-Change-Number: 22869 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>