<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22839">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS<br><br>TEST=System is able to power on after reconnecting power system.<br><br>Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/pmc.c<br>1 file changed, 42 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22839/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c<br>index 91b319c..5f3ef2b 100644<br>--- a/src/soc/intel/skylake/pmc.c<br>+++ b/src/soc/intel/skylake/pmc.c<br>@@ -15,6 +15,7 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>+#include <bootstate.h><br> #include <chip.h><br> #include <console/console.h><br> #include <device/device.h><br>@@ -73,9 +74,24 @@<br>      REG_SCRIPT_END<br> };<br> <br>+/*<br>+ * Determines what state to go to when power is reapplied<br>+ * after a power failure (G3 State)<br>+ */<br>+static void pmc_set_afterg3(struct device *dev, int s5pwr)<br>+{<br>+ uint8_t reg8;<br>+<br>+     reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B);<br>+   if (s5pwr == MAINBOARD_POWER_ON)<br>+             reg8 &= ~1;<br>+      else<br>+         reg8 |= 1;<br>+   pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);<br>+}<br>+<br> static void pch_power_options(struct device *dev)<br> {<br>-    u16 reg16;<br>    const char *state;<br> <br>         /* Get the chip configuration */<br>@@ -91,25 +107,20 @@<br>        /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/<br>      //get_option(&pwr_on, "power_on_after_fail");<br>   pwr_on = MAINBOARD_POWER_ON;<br>- reg16 = pci_read_config16(dev, GEN_PMCON_B);<br>- reg16 &= 0xfffe;<br>  switch (pwr_on) {<br>     case MAINBOARD_POWER_OFF:<br>-            reg16 |= 1;<br>           state = "off";<br>              break;<br>        case MAINBOARD_POWER_ON:<br>-             reg16 &= ~1;<br>              state = "on";<br>               break;<br>        case MAINBOARD_POWER_KEEP:<br>-           reg16 &= ~1;<br>              state = "state keep";<br>               break;<br>        default:<br>              state = "undefined";<br>        }<br>-    pci_write_config16(dev, GEN_PMCON_B, reg16);<br>+ pmc_set_afterg3(dev, pwr_on);<br>         printk(BIOS_INFO, "Set power %s after power failure.\n", state);<br> <br>         /* Set up GPE configuration. */<br>@@ -178,4 +189,28 @@<br>         /* Clear registers that contain write-1-to-clear bits. */<br>     reg_script_run_on_dev(dev, pmc_write1_to_clear_script);<br> }<br>+<br>+/*<br>+ * Set PMC register to know which state system should be after<br>+ * power reapplied<br>+ */<br>+void pmc_soc_restore_power_failiure(void)<br>+{<br>+      pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_ON);<br>+}<br>+<br>+static void pm1_enable_pwrbtn_smi(void *unused)<br>+{<br>+       /*<br>+    * Enable power button SMI only before jumping to payload. This ensures<br>+       * that:<br>+      * 1. Power button SMI is enabled only after coreboot is done.<br>+        * 2. On resume path, power button SMI is not enabled and thus avoids<br>+         * any shutdowns because of power button presses due to power button<br>+  * press in resume path.<br>+      */<br>+  pmc_update_pm1_enable(PWRBTN_EN);<br>+}<br>+<br>+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);<br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22839">change 22839</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22839"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 </div>
<div style="display:none"> Gerrit-Change-Number: 22839 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>