<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22819">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Enable LPC IO Decoding on PCR<br><br>According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4),<br>section 2.5.1.6, it is a requirement to program the same<br>value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h"<br>to fully enable the Lpc IO enable decoding which is missing in<br>current source.<br><br>Without above changes, Skylake Saddlebrook platform with using<br>SIO does not able to boot.<br><br>Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173<br>Signed-off-by: praveen <praveenx.hodagatta.pranesh@intel.com><br>---<br>M src/soc/intel/skylake/lpc.c<br>1 file changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/22819/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c<br>index bd6fbc4..b5105e4 100644<br>--- a/src/soc/intel/skylake/lpc.c<br>+++ b/src/soc/intel/skylake/lpc.c<br>@@ -31,6 +31,7 @@<br> #include <reg_script.h><br> #include <soc/iomap.h><br> #include <soc/pcr_ids.h><br>+#include <soc/intel/common/block/lpc/lpc_def.h><br> <br> /**<br>   PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF<br>@@ -81,11 +82,17 @@<br> <br> void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)<br> {<br>+      uint16_t lpc_en;<br>+<br>   /* Mirror these same settings in DMI PCR */<br>   pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);<br>        pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);<br>        pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);<br>        pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);<br>+<br>+    /* LPC IO Decode Enable  */<br>+  lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);<br>+     pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);<br> }<br> <br> static const struct reg_script pch_misc_init_script[] = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/22819">change 22819</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22819"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 </div>
<div style="display:none"> Gerrit-Change-Number: 22819 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>