<p>Tobias Diedrich has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22808">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nuvoton/nct6776: Add ACPI declarations<br><br>Add ACPI declarations to be incorporated into ACPI tables for<br>mainboards with this super I/O.<br><br>Tested on Intel NUC DCP847SKE, Linux 4.13.14.<br>SuperIO resources show up as reserved in /proc/ioports and friends.<br><br>Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f<br>Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>---<br>M src/mainboard/intel/dcp847ske/acpi/superio.asl<br>A src/superio/nuvoton/nct6776/acpi/superio.asl<br>2 files changed, 193 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/22808/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl<br>index 09f905e..aefb51d 100644<br>--- a/src/mainboard/intel/dcp847ske/acpi/superio.asl<br>+++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl<br>@@ -1 +1,28 @@<br>-/* Dummy file required by pch.asl - No license necessary. */<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 secunet Security Networks AG<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#undef SUPERIO_DEV<br>+#undef SUPERIO_PNP_BASE<br>+#define SUPERIO_DEV SIO0<br>+#define SUPERIO_PNP_BASE 0x4e<br>+<br>+#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)<br>+#define NCT6776_SHOW_SP1 1<br>+#endif<br>+#define NCT6776_SHOW_HWM 1<br>+#define NCT6776_SHOW_GPIO 1<br>+<br>+#include "superio/nuvoton/nct6776/acpi/superio.asl"<br>diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl<br>new file mode 100644<br>index 0000000..155917d<br>--- /dev/null<br>+++ b/src/superio/nuvoton/nct6776/acpi/superio.asl<br>@@ -0,0 +1,165 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de><br>+ * Copyright (C) 2013, 2016 secunet Security Networks AG<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * Include this file into a mainboard's DSDT _SB device tree and it will<br>+ * expose the NCT6886 SuperIO and some of its functionality.<br>+ *<br>+ * It allows the change of IO ports, IRQs and DMA settings on logical<br>+ * devices, disabling and reenabling logical devices.<br>+ *<br>+ * LDN State<br>+ * 0x2 SP1 Implemented, untested<br>+ * 0x5 KBCK Implemented, untested<br>+ * 0x8 GPIO Implemented, untested<br>+ * 0xb HWM Implemented, untested<br>+ *<br>+ * Controllable through preprocessor defines:<br>+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)<br>+ * SUPERIO_PNP_BASE I/O address of the first PnP configuration register<br>+ * NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed.<br>+ * NCT6776_SHOW_KBCK If defined, the Keyboard Controller will be exposed.<br>+ * NCT6776_SHOW_GPIO If defined, GPIO support will be exposed.<br>+ * NCT6776_SHOW_HWM If defined, the Environment Controller will be exposed.<br>+ */<br>+<br>+#undef SUPERIO_CHIP_NAME<br>+#define SUPERIO_CHIP_NAME NCT6776<br>+#include <superio/acpi/pnp.asl><br>+<br>+#undef PNP_DEFAULT_PSC<br>+#define PNP_DEFAULT_PSC Return (0) /* no power management */<br>+<br>+Device(SUPERIO_DEV) {<br>+ Name (_HID, EisaId("PNP0A05"))<br>+ Name (_STR, Unicode("Nuvoton NCT6776 Super I/O"))<br>+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))<br>+<br>+ /* SuperIO configuration ports */<br>+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)<br>+ Field (CREG, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PNP_ADDR_REG, 8,<br>+ PNP_DATA_REG, 8,<br>+ }<br>+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x07),<br>+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */<br>+<br>+ Offset (0x30),<br>+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */<br>+ ACT1, 1, /* Logical device activation */<br>+ ACT2, 1, /* Logical device activation */<br>+ ACT3, 1, /* Logical device activation */<br>+ ACT4, 1, /* Logical device activation */<br>+ ACT5, 1, /* Logical device activation */<br>+ ACT6, 1, /* Logical device activation */<br>+ ACT7, 1, /* Logical device activation */<br>+<br>+ Offset (0x60),<br>+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */<br>+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */<br>+ Offset (0x62),<br>+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */<br>+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */<br>+ Offset (0x64),<br>+ PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */<br>+ PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */<br>+<br>+ Offset (0x70),<br>+ PNP_IRQ0, 8, /* First IRQ */<br>+ }<br>+<br>+ Method (_CRS)<br>+ {<br>+ /* Announce the used I/O ports to the OS */<br>+ Return (ResourceTemplate () {<br>+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)<br>+ })<br>+ }<br>+<br>+ #undef PNP_ENTER_MAGIC_1ST<br>+ #undef PNP_ENTER_MAGIC_2ND<br>+ #undef PNP_ENTER_MAGIC_3RD<br>+ #undef PNP_ENTER_MAGIC_4TH<br>+ #undef PNP_EXIT_MAGIC_1ST<br>+ #undef PNP_EXIT_SPECIAL_REG<br>+ #undef PNP_EXIT_SPECIAL_VAL<br>+ #define PNP_ENTER_MAGIC_1ST 0x87<br>+ #define PNP_ENTER_MAGIC_2ND 0x87<br>+ #define PNP_EXIT_MAGIC_1ST 0xaa<br>+ #include <superio/acpi/pnp_config.asl><br>+<br>+#ifdef NCT6776_SHOW_SP1<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_DDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #undef SUPERIO_UART_PM_VAL<br>+ #undef SUPERIO_UART_PM_LDN<br>+ #define SUPERIO_UART_LDN 2<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+#ifdef NCT6776_SHOW_KBC<br>+ #undef SUPERIO_KBC_LDN<br>+ #undef SUPERIO_KBC_PS2M<br>+ #undef SUPERIO_KBC_PS2LDN<br>+ #define SUPERIO_KBC_LDN 5<br>+ #include <superio/acpi/pnp_kbc.asl><br>+#endif<br>+<br>+#ifdef NCT6776_SHOW_HWM<br>+ #undef SUPERIO_PNP_HID<br>+ #undef SUPERIO_PNP_LDN<br>+ #undef SUPERIO_PNP_DDN<br>+ #undef SUPERIO_PNP_PM_REG<br>+ #undef SUPERIO_PNP_PM_VAL<br>+ #undef SUPERIO_PNP_PM_LDN<br>+ #undef SUPERIO_PNP_IO0<br>+ #undef SUPERIO_PNP_IO1<br>+ #undef SUPERIO_PNP_IO2<br>+ #undef SUPERIO_PNP_IRQ0<br>+ #undef SUPERIO_PNP_IRQ1<br>+ #undef SUPERIO_PNP_DMA<br>+ #define SUPERIO_PNP_LDN 11<br>+ #define SUPERIO_PNP_IO0 0x08, 0x08<br>+ #define SUPERIO_PNP_IO1 0x08, 0x08<br>+ #define SUPERIO_PNP_IRQ0<br>+ #include <superio/acpi/pnp_generic.asl><br>+#endif<br>+<br>+#ifdef NCT6776_SHOW_GPIO<br>+ #undef SUPERIO_PNP_HID<br>+ #undef SUPERIO_PNP_LDN<br>+ #undef SUPERIO_PNP_DDN<br>+ #undef SUPERIO_PNP_PM_REG<br>+ #undef SUPERIO_PNP_PM_VAL<br>+ #undef SUPERIO_PNP_PM_LDN<br>+ #undef SUPERIO_PNP_IO0<br>+ #undef SUPERIO_PNP_IO1<br>+ #undef SUPERIO_PNP_IO2<br>+ #undef SUPERIO_PNP_IRQ0<br>+ #undef SUPERIO_PNP_IRQ1<br>+ #undef SUPERIO_PNP_DMA<br>+ #undef PNP_DEVICE_ACTIVE<br>+ #define PNP_DEVICE_ACTIVE ACT3<br>+ #define SUPERIO_PNP_LDN 8<br>+ #define SUPERIO_PNP_IO0 0x08, 0x08<br>+ #include <superio/acpi/pnp_generic.asl><br>+#endif<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22808">change 22808</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f </div>
<div style="display:none"> Gerrit-Change-Number: 22808 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tobias Diedrich <ranma+coreboot@tdiedrich.de> </div>