<p>Tobias Diedrich has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22806">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/sandybridge: Add RAM voltage hooks<br><br>Some boards support low-voltage DDR3.<br><br>This adds a hook for native raminit that is called before ram training<br>and allows the romstage to set the RAM voltage first.<br><br>Tested:<br>- Measured voltage on Intel NUC DCP847SKE changes from 1.5V to 1.35V<br> when the RAM SPD claims support<br><br>Known issues:<br>- Native raminit fails timC calibration with the RAM I have<br>- Non-native raminit will continue to use the default voltage<br><br>Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817<br>Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>---<br>M src/mainboard/intel/dcp847ske/romstage.c<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>M src/northbridge/intel/sandybridge/raminit_common.h<br>M src/northbridge/intel/sandybridge/raminit_ivy.c<br>M src/northbridge/intel/sandybridge/raminit_native.h<br>M src/northbridge/intel/sandybridge/raminit_sandy.c<br>6 files changed, 32 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/22806/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c<br>index ad31bba..cef6094 100644<br>--- a/src/mainboard/intel/dcp847ske/romstage.c<br>+++ b/src/mainboard/intel/dcp847ske/romstage.c<br>@@ -16,7 +16,9 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <console/console.h><br> #include <stdint.h><br>+#include <southbridge/intel/common/gpio.h><br> #include <northbridge/intel/sandybridge/sandybridge.h><br> #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)<br> #include <northbridge/intel/sandybridge/raminit_native.h><br>@@ -24,7 +26,20 @@<br> #include <northbridge/intel/sandybridge/raminit.h><br> #endif<br> <br>-#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)<br>+#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)<br>+void mainboard_set_dram_voltage(dimm_flags_t flags)<br>+{<br>+ if (flags.operable_1_35V) {<br>+ // GPIO8 default from gpio.c is LOW (1.5V).<br>+ // Set to HIGH to lower ram voltage to 1.35V.<br>+ set_gpio(8, 1);<br>+ } else if (!flags.operable_1_50V) {<br>+ // 1.50V _should_ be supported by any DDR3 ram that fits<br>+ // the connector...<br>+ printk(BIOS_ERR, "RAM does not support 1.35V or 1.5V!\n");<br>+ }<br>+}<br>+#else<br> void mainboard_fill_pei_data(struct pei_data *pei_data)<br> {<br> struct pei_data pei_data_template = {<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c<br>index eaef5f7..92bd9c5 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.c<br>@@ -138,12 +138,16 @@<br> dimm_info *dimms = &ctrl->info;<br> <br> ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1;<br>+ ctrl->flags.raw = 0xffffffff;<br> valid_dimms = 0;<br> FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) {<br> const dimm_attr *dimm = &dimms->dimm[channel][slot];<br> if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3)<br> continue;<br> valid_dimms++;<br>+<br>+ /* Find common flags */<br>+ ctrl->flags.raw &= dimm->flags.raw;<br> <br> /* Find all possible CAS combinations */<br> ctrl->cas_supported &= dimm->cas_supported;<br>@@ -3363,3 +3367,7 @@<br> <br> write32(DEFAULT_MCHBAR + 0x4ea8, 0);<br> }<br>+<br>+void __attribute__((weak)) mainboard_set_dram_voltage(dimm_flags_t flags)<br>+{<br>+}<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h<br>index ab6e592..c9f5c25 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.h<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.h<br>@@ -81,6 +81,7 @@<br> /* DDR base_freq = 100 Mhz / 133 Mhz */<br> u8 base_freq;<br> <br>+ dimm_flags_t flags;<br> u16 cas_supported;<br> /* tLatencies are in units of ns, scaled by x256 */<br> u32 tCK;<br>diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c<br>index 675ac71..3df68c5 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_ivy.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c<br>@@ -646,6 +646,9 @@<br> dram_dimm_mapping(ctrl);<br> }<br> <br>+ /* Set DRAM voltage */<br>+ mainboard_set_dram_voltage(ctrl->flags);<br>+<br> /* Set MCU frequency */<br> dram_freq(ctrl);<br> <br>diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h<br>index 2a91772..4744edd 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_native.h<br>+++ b/src/northbridge/intel/sandybridge/raminit_native.h<br>@@ -22,5 +22,6 @@<br> /* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */<br> void read_spd(spd_raw_data *spd, u8 addr, bool id_only);<br> void mainboard_get_spd(spd_raw_data *spd, bool id_only);<br>+void mainboard_set_dram_voltage(dimm_flags_t flags);<br> <br> #endif /* RAMINIT_H */<br>diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c<br>index 3acc563..231159f 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_sandy.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c<br>@@ -416,6 +416,9 @@<br> dram_dimm_mapping(ctrl);<br> }<br> <br>+ /* Set DRAM voltage */<br>+ mainboard_set_dram_voltage(ctrl->flags);<br>+<br> /* Set MCU frequency */<br> dram_freq(ctrl);<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22806">change 22806</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817 </div>
<div style="display:none"> Gerrit-Change-Number: 22806 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tobias Diedrich <ranma+coreboot@tdiedrich.de> </div>