<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22803">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common: Add function to automatically generate ACPI PIRQ<br><br>With the RCBA DxxIR registers on reset default the pins are mapped<br>quite straightforwardly namely pinA -> linkA, pinB -> linkB, pinC -><br>linkC, pinD -> linkD. Although this might not be optimal for<br>performance, it does provide a good working default.<br><br>This function generates PIRQ ACPI tables automatically based on the<br>previous assumption.<br><br>Change-Id: I2b5d68adabf0840162c6f295af8d10d8d3007a34<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/common/Kconfig<br>M src/southbridge/intel/common/Makefile.inc<br>A src/southbridge/intel/common/acpi_pirq_gen.c<br>A src/southbridge/intel/common/acpi_pirq_gen.h<br>4 files changed, 145 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/22803/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig<br>index 304ecbf..8ea8c77 100644<br>--- a/src/southbridge/intel/common/Kconfig<br>+++ b/src/southbridge/intel/common/Kconfig<br>@@ -11,6 +11,9 @@<br> config HAVE_INTEL_CHIPSET_LOCKDOWN<br> def_bool n<br> <br>+config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN<br>+ def_bool n<br>+<br> config INTEL_CHIPSET_LOCKDOWN<br> depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS<br> #ChromeOS's payload seems to handle finalization on its on.<br>diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc<br>index 5810394..aae5c83 100644<br>--- a/src/southbridge/intel/common/Makefile.inc<br>+++ b/src/southbridge/intel/common/Makefile.inc<br>@@ -28,4 +28,6 @@<br> romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c<br> ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c<br> <br>+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN) += acpi_pirq_gen.c<br>+<br> endif<br>diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c<br>new file mode 100644<br>index 0000000..d5a17d7<br>--- /dev/null<br>+++ b/src/southbridge/intel/common/acpi_pirq_gen.c<br>@@ -0,0 +1,119 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpigen.h><br>+#include <arch/io.h><br>+#include <device/pci_def.h><br>+<br>+#include "acpi_pirq_gen.h"<br>+<br>+static int count_different_pirq(void)<br>+{<br>+ device_t irq_dev;<br>+ u8 prev_int_pin = 0;<br>+ u32 prev_pci_dev = 0;<br>+ int num_devs = 0;<br>+<br>+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {<br>+ u8 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);<br>+ u32 pci_dev = (irq_dev->path.pci.devfn >> 3) & 0x1f;<br>+<br>+ if (irq_dev->bus->secondary != 0)<br>+ continue;<br>+ if (int_pin == 0 || int_pin > 4)<br>+ continue;<br>+ /* Avoid dublicate entries */<br>+ if (prev_pci_dev == pci_dev && prev_int_pin == int_pin) {<br>+ continue;<br>+ } else {<br>+ prev_int_pin = int_pin;<br>+ prev_pci_dev = pci_dev;<br>+ }<br>+ num_devs++;<br>+ }<br>+ return num_devs;<br>+}<br>+<br>+void gen_def_acpi_pirq(void)<br>+{<br>+ device_t irq_dev;<br>+ u8 prev_int_pin = 0;<br>+ u32 prev_pci_dev = 0;<br>+ int num_devs = count_different_pirq();<br>+ const char *link_list[4] = {"\\_SB.PCI0.LPCB.LNKA",<br>+ "\\_SB.PCI0.LPCB.LNKB",<br>+ "\\_SB.PCI0.LPCB.LNKC",<br>+ "\\_SB.PCI0.LPCB.LNKD"};<br>+<br>+ acpigen_write_scope("\\_SB.PCI0");<br>+ acpigen_write_method("_PRT", 0);<br>+ acpigen_write_if();<br>+ acpigen_emit_namestring("PICM");<br>+ acpigen_emit_byte(RETURN_OP);<br>+ acpigen_write_package(num_devs);<br>+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {<br>+ u8 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);<br>+ u32 pci_dev = (irq_dev->path.pci.devfn >> 3) & 0x1f;<br>+<br>+ if (irq_dev->bus->secondary != 0)<br>+ continue;<br>+ if (int_pin == 0 || int_pin > 4)<br>+ continue;<br>+ /* Avoid dublicate entries */<br>+ if (prev_pci_dev == pci_dev && prev_int_pin == int_pin) {<br>+ continue;<br>+ } else {<br>+ prev_int_pin = int_pin;<br>+ prev_pci_dev = pci_dev;<br>+ }<br>+ acpigen_write_package(4);<br>+ acpigen_write_dword((pci_dev << 16) | 0xffff);<br>+ acpigen_write_dword(int_pin - 1);<br>+ acpigen_write_dword(0);<br>+ acpigen_write_dword(16 + (int_pin - 1));<br>+ acpigen_pop_len();<br>+ }<br>+ acpigen_pop_len(); /* package */<br>+ acpigen_pop_len(); /* if PICM */<br>+ acpigen_write_else();<br>+ acpigen_emit_byte(RETURN_OP);<br>+ acpigen_write_package(num_devs);<br>+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {<br>+ u8 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);<br>+ u32 pci_dev = (irq_dev->path.pci.devfn >> 3) & 0x1f;<br>+<br>+ if (irq_dev->bus->secondary != 0)<br>+ continue;<br>+ if (int_pin == 0 || int_pin > 4)<br>+ continue;<br>+ /* Avoid dublicate entries */<br>+ if (prev_pci_dev == pci_dev && prev_int_pin == int_pin) {<br>+ continue;<br>+ } else {<br>+ prev_int_pin = int_pin;<br>+ prev_pci_dev = pci_dev;<br>+ }<br>+ acpigen_write_package(4);<br>+ acpigen_write_dword((pci_dev << 16) | 0xffff);<br>+ acpigen_write_dword(int_pin - 1);<br>+ acpigen_emit_namestring(link_list[int_pin - 1]);<br>+ acpigen_write_dword(0);<br>+ acpigen_pop_len();<br>+ }<br>+ acpigen_pop_len(); /* package */<br>+ acpigen_pop_len(); /* else PICM */<br>+ acpigen_pop_len(); /* _PRT */<br>+ acpigen_pop_len(); /* \_SB */<br>+}<br>diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h<br>new file mode 100644<br>index 0000000..a3f0609<br>--- /dev/null<br>+++ b/src/southbridge/intel/common/acpi_pirq_gen.h<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H<br>+#define INTEL_COMMON_ACPI_PIRQ_GEN_H<br>+<br>+void gen_def_acpi_pirq(void);<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22803">change 22803</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22803"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2b5d68adabf0840162c6f295af8d10d8d3007a34 </div>
<div style="display:none"> Gerrit-Change-Number: 22803 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>