<p>Abhay Kumar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22799">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics.<br><br>TEST=Edp should come up in normal mode.<br><br>Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef<br>Signed-off-by: Abhay Kumar <abhay.kumar@intel.com><br>---<br>M src/soc/intel/cannonlake/graphics.c<br>1 file changed, 37 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/22799/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c<br>index 5cf0ec8..6e1142a 100644<br>--- a/src/soc/intel/cannonlake/graphics.c<br>+++ b/src/soc/intel/cannonlake/graphics.c<br>@@ -21,12 +21,49 @@<br> #include <device/pci.h><br> #include <drivers/intel/gma/opregion.h><br> #include <intelblocks/graphics.h><br>+#include <drivers/intel/gma/i915_reg.h><br> <br> uintptr_t fsp_soc_get_igd_bar(void)<br> {<br> return graphics_get_memory_base();<br> }<br> <br>+void graphics_soc_init(struct device *dev)<br>+{<br>+ u32 ddi_buf_ctl;<br>+<br>+ /*<br>+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.<br>+ * This will allow the kernel to use 4-lane eDP links properly<br>+ * if the VBIOS or GOP driver does not execute.<br>+ */<br>+ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);<br>+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {<br>+ ddi_buf_ctl |= DDI_A_4_LANES;<br>+ graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);<br>+ }<br>+<br>+ /*<br>+ * GFX PEIM module inside FSP binary is taking care of graphics<br>+ * initialization based on INTEL_GMA_ADD_VBT_DATA_FILE Kconfig<br>+ * option and input VBT file. Hence no need to load/execute legacy VGA<br>+ * OpROM in order to initialize GFX.<br>+ *<br>+ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN<br>+ * Kconfig to perform GFX initialization through VGA OpRom.<br>+ */<br>+ if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))<br>+ return;<br>+<br>+ /* IGD needs to Bus Master */<br>+ u32 reg32 = pci_read_config32(dev, PCI_COMMAND);<br>+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;<br>+ pci_write_config32(dev, PCI_COMMAND, reg32);<br>+<br>+ /* Initialize PCI device, load/execute BIOS Option ROM */<br>+ pci_dev_init(dev);<br>+}<br>+<br> uintptr_t graphics_soc_write_acpi_opregion(struct device *device,<br> uintptr_t current, struct acpi_rsdp *rsdp)<br> {<br></pre><p>To view, visit <a href="https://review.coreboot.org/22799">change 22799</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22799"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef </div>
<div style="display:none"> Gerrit-Change-Number: 22799 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Abhay Kumar <abhay.kumar@intel.com> </div>