<p>Julius Werner would like David Schneider and Philip Chen to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22791">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/gru: Stop mucking with unused I2S0 pins in codec config<br><br>Due to a schematic error, our code was written to configure more I2S0<br>pins than are actually used. We're also pinmuxing the whole bank of pins<br>over to the I2S controller even though we don't need them all. Restrict<br>the GPIO initialization and pinmuxing to the pins we really need so the<br>other ones can be correctly used as SKU ID pins on Scarlet.<br><br>Also, move the "audio" IO voltage domain selection to the other such<br>selections in the bootblock, since that covers two whole banks of GPIOs<br>and there's no guarantee that they're all used for audio (and thus not<br>needed before ramstage).<br><br>BUG=b:69373077<br>TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2.<br><br>Change-Id: I9314617e725fe83d254984529f269d4442e736f1<br>Signed-off-by: Julius Werner <jwerner@chromium.org><br>---<br>M src/mainboard/google/gru/bootblock.c<br>M src/mainboard/google/gru/mainboard.c<br>M src/soc/rockchip/rk3399/include/soc/grf.h<br>3 files changed, 7 insertions(+), 23 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/22791/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c<br>index a18a61c..0013414 100644<br>--- a/src/mainboard/google/gru/bootblock.c<br>+++ b/src/mainboard/google/gru/bootblock.c<br>@@ -31,20 +31,10 @@<br> <br> void bootblock_mainboard_early_init(void)<br> {<br>- /* Let gpio2ab io domains works at 1.8V.<br>- *<br>- * If io_vsel[0] == 0(default value), gpio2ab io domains is 3.0V<br>- * powerd by APIO2_VDD, otherwise, 1.8V supplied by APIO2_VDDPST.<br>- * But from the schematic of kevin rev0, the APIO2_VDD and<br>- * APIO2_VDDPST both are 1.8V(intentionally?).<br>- *<br>- * So, by default, CPU1_SDIO_PWREN(GPIO2_A2) can't output 3.0V<br>- * because the supply is 1.8V.<br>- * Let ask GPIO2_A2 output 1.8V to make GPIO interal logic happy.<br>- */<br>- write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0));<br>-<br>- /* Scarlet-based gpio4cd iodomain is 1.8V */<br>+ /* Configure all programmable IO voltage domains (3D/4A and 2A/2B) early<br>+ so that we know we can use our GPIOs reliably in following code. */<br>+ write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1 | 1 << 0));<br>+ /* On Scarlet-based boards, the 4C/4D domain is 1.8V (on others 3.0V) */<br> if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))<br> write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3));<br> <br>diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c<br>index 9a241f5..1a24862 100644<br>--- a/src/mainboard/google/gru/mainboard.c<br>+++ b/src/mainboard/google/gru/mainboard.c<br>@@ -218,17 +218,12 @@<br> gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */<br> gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */<br> gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */<br>- gpio_input(GPIO(3, D, 4)); /* I2S0_SDI1 remove pull-up */<br>- /* GPIO3_D5 (I2S0_SDI2SDO2) not connected */<br>- gpio_input(GPIO(3, D, 6)); /* I2S0_SDO1 remove pull-up */<br>+ /* GPIOs 3_D4 - 3_D6 not used for I2S and are SKU ID pins on Scarlet. */<br> gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */<br> gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */<br> <br>- write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0);<br>+ write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0_SD0);<br> write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);<br>-<br>- /* AUDIO IO domain 1.8V voltage selection */<br>- write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1));<br> <br> if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))<br> gpio_output(GPIO_P18V_AUDIO_PWREN, 1);<br>diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h<br>index 8e12007..9bda967 100644<br>--- a/src/soc/rockchip/rk3399/include/soc/grf.h<br>+++ b/src/soc/rockchip/rk3399/include/soc/grf.h<br>@@ -356,8 +356,7 @@<br> #define IOMUX_I2C0_SCL RK_CLRSETBITS(3 << 0, 2 << 0)<br> #define IOMUX_I2C0_SDA RK_CLRSETBITS(3 << 14, 2 << 14)<br> <br>-#define IOMUX_I2S0 RK_SETBITS(1 << 14 | 1 << 12 | 1 << 10 | 1 << 8 |\<br>- 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0)<br>+#define IOMUX_I2S0_SD0 RK_SETBITS(1 << 14 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0)<br> #define IOMUX_I2SCLK RK_SETBITS(1 << 0)<br> <br> #define IOMUX_PWM_0 RK_SETBITS(1 << 4)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22791">change 22791</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22791"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9314617e725fe83d254984529f269d4442e736f1 </div>
<div style="display:none"> Gerrit-Change-Number: 22791 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julius Werner <jwerner@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: David Schneider <dnschneid@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Philip Chen <philipchen@chromium.org> </div>