<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22785">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge/hudson: Replace "\t" from name table<br><br>Arrays intr_types[] (hudson) and its replacement irq_association[]<br>(stoneyridge) use "\t" (tab) to force alignment when printing. As the<br>checkpatch.pl program expands "\t" when testing, it can cause a "more<br>than 80 characters" error when committing, while the actual line is less<br>than 80 characters.<br><br>Replacing "\t" with the appropriate number of white spaces will have the<br>double benefit of avoiding the "more than 80 characters" error and<br>creating an alignment within the strings declarations.<br><br>BUG=b:70344551<br>TEST=stoneyridge: Build and boot, record output of irq routing and<br>verify alignment. hudson: None (no board to test).<br><br>Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/southbridge.c<br>M src/southbridge/amd/pi/hudson/amd_pci_int_types.h<br>2 files changed, 56 insertions(+), 50 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/22785/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index f8e06b3..d27f503 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -40,46 +40,46 @@<br> * Order is not important.<br> */<br> const static struct irq_idx_name irq_association[] = {<br>- { PIRQ_A, "INTA#\t" },<br>- { PIRQ_B, "INTB#\t" },<br>- { PIRQ_C, "INTC#\t" },<br>- { PIRQ_D, "INTD#\t" },<br>- { PIRQ_E, "INTE#\t" },<br>- { PIRQ_F, "INTF#\t" },<br>- { PIRQ_G, "INTG#\t" },<br>- { PIRQ_H, "INTH#\t" },<br>- { PIRQ_MISC, "Misc\t" },<br>- { PIRQ_MISC0, "Misc0\t" },<br>- { PIRQ_MISC1, "Misc1\t" },<br>- { PIRQ_MISC2, "Misc2\t" },<br>+ { PIRQ_A, "INTA# " },<br>+ { PIRQ_B, "INTB# " },<br>+ { PIRQ_C, "INTC# " },<br>+ { PIRQ_D, "INTD# " },<br>+ { PIRQ_E, "INTE# " },<br>+ { PIRQ_F, "INTF# " },<br>+ { PIRQ_G, "INTG# " },<br>+ { PIRQ_H, "INTH# " },<br>+ { PIRQ_MISC, "Misc " },<br>+ { PIRQ_MISC0, "Misc0 " },<br>+ { PIRQ_MISC1, "Misc1 " },<br>+ { PIRQ_MISC2, "Misc2 " },<br> { PIRQ_SIRQA, "Ser IRQ INTA" },<br> { PIRQ_SIRQB, "Ser IRQ INTB" },<br> { PIRQ_SIRQC, "Ser IRQ INTC" },<br> { PIRQ_SIRQD, "Ser IRQ INTD" },<br>- { PIRQ_SCI, "SCI\t" },<br>- { PIRQ_SMBUS, "SMBUS\t" },<br>- { PIRQ_ASF, "ASF\t" },<br>- { PIRQ_HDA, "HDA\t" },<br>- { PIRQ_FC, "FC\t\t" },<br>- { PIRQ_PMON, "PerMon\t" },<br>- { PIRQ_SD, "SD\t\t" },<br>- { PIRQ_SDIO, "SDIO\t" },<br>- { PIRQ_IMC0, "IMC INT0\t" },<br>- { PIRQ_IMC1, "IMC INT1\t" },<br>- { PIRQ_IMC2, "IMC INT2\t" },<br>- { PIRQ_IMC3, "IMC INT3\t" },<br>- { PIRQ_IMC4, "IMC INT4\t" },<br>- { PIRQ_IMC5, "IMC INT5\t" },<br>- { PIRQ_EHCI, "EHCI\t" },<br>- { PIRQ_XHCI, "XHCI\t" },<br>- { PIRQ_SATA, "SATA\t" },<br>- { PIRQ_GPIO, "GPIO\t" },<br>- { PIRQ_I2C0, "I2C0\t" },<br>- { PIRQ_I2C1, "I2C1\t" },<br>- { PIRQ_I2C2, "I2C2\t" },<br>- { PIRQ_I2C3, "I2C3\t" },<br>- { PIRQ_UART0, "UART0\t" },<br>- { PIRQ_UART1, "UART1\t" },<br>+ { PIRQ_SCI, "SCI " },<br>+ { PIRQ_SMBUS, "SMBUS " },<br>+ { PIRQ_ASF, "ASF " },<br>+ { PIRQ_HDA, "HDA " },<br>+ { PIRQ_FC, "FC " },<br>+ { PIRQ_PMON, "PerMon " },<br>+ { PIRQ_SD, "SD " },<br>+ { PIRQ_SDIO, "SDIO " },<br>+ { PIRQ_IMC0, "IMC INT0 " },<br>+ { PIRQ_IMC1, "IMC INT1 " },<br>+ { PIRQ_IMC2, "IMC INT2 " },<br>+ { PIRQ_IMC3, "IMC INT3 " },<br>+ { PIRQ_IMC4, "IMC INT4 " },<br>+ { PIRQ_IMC5, "IMC INT5 " },<br>+ { PIRQ_EHCI, "EHCI " },<br>+ { PIRQ_XHCI, "XHCI " },<br>+ { PIRQ_SATA, "SATA " },<br>+ { PIRQ_GPIO, "GPIO " },<br>+ { PIRQ_I2C0, "I2C0 " },<br>+ { PIRQ_I2C1, "I2C1 " },<br>+ { PIRQ_I2C2, "I2C2 " },<br>+ { PIRQ_I2C3, "I2C3 " },<br>+ { PIRQ_UART0, "UART0 " },<br>+ { PIRQ_UART1, "UART1 " },<br> };<br> <br> /*<br>diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h<br>index f898907..b90dc4d 100644<br>--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h<br>+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h<br>@@ -17,23 +17,29 @@<br> #define AMD_PCI_INT_TYPES_H<br> <br> const char * intr_types[] = {<br>- [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",<br>- [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",<br>- [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",<br>- [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",<br>- [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",<br>- [0x7F] = "RSVD\t",<br>+ [0x00] = "INTA# ", "INTB# ", "INTC# ", "INTD# ",<br>+ "INTE# ", "INTF# ", "INTG# ", "INTH# ",<br>+ [0x08] = "Misc ", "Misc0 ", "Misc1 ", "Misc2 ",<br>+ "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",<br>+ [0x10] = "SCI ", "SMBUS0 ", "ASF ", "HDA ",<br>+ "FC ", "GEC ", "PerMon ", "SD ",<br>+ [0x20] = "IMC INT0 ", "IMC INT1 ", "IMC INT2 ", "IMC INT3 ",<br>+ "IMC INT4 ", "IMC INT5 ",<br>+ [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB",<br>+ "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",<br>+ [0x7F] = "RSVD ",<br> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)<br>- [0x40] = "RSVD\t", "SATA\t",<br>- [0x60] = "RSVD\t", "RSVD\t", "GPIO\t",<br>+ [0x40] = "RSVD ", "SATA ",<br>+ [0x60] = "RSVD ", "RSVD ", "GPIO ",<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)<br>- [0x40] = "IDE\t", "SATA\t",<br>- [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",<br>+ [0x40] = "IDE ", "SATA ",<br>+ [0x50] = "GPPInt0 ", "GPPInt1 ", "GPPInt2 ", "GPPInt3 ",<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)<br>- [0x40] = "IDE\t", "SATA\t",<br>- [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",<br>- [0x62] = "GPIO\t",<br>- [0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",<br>+ [0x40] = "IDE ", "SATA ",<br>+ [0x50] = "GPPInt0 ", "GPPInt1 ", "GPPInt2 ", "GPPInt3 ",<br>+ [0x62] = "GPIO ",<br>+ [0x70] = "I2C0 ", "I2C1 ", "I2C2 ", "I2C3 ",<br>+ "UART0 ", "UART1 ",<br> #endif<br> };<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22785">change 22785</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22785"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a </div>
<div style="display:none"> Gerrit-Change-Number: 22785 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>