<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22771">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Clean up UART code<br><br>Clean up and move UART related code under a single uart.c file.<br><br>Change-Id: I7eea910e065242689e87adac41281131674b39af<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/uart.c<br>D src/soc/intel/cannonlake/uart_pch.c<br>3 files changed, 47 insertions(+), 68 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/22771/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 076e76b..61318a4 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -47,7 +47,6 @@<br> ramstage-y += spi.c<br> ramstage-y += systemagent.c<br> ramstage-$(CONFIG_UART_DEBUG) += uart.c<br>-ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c<br> ramstage-y += vr_config.c<br> ramstage-y += sd.c<br> <br>@@ -55,7 +54,6 @@<br> smm-y += pmutil.c<br> smm-y += smihandler.c<br> smm-$(CONFIG_UART_DEBUG) += uart.c<br>-smm-$(CONFIG_UART_DEBUG) += uart_pch.c<br> <br> postcar-y += memmap.c<br> postcar-y += pmutil.c<br>diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c<br>index 66883ec..21b6417 100644<br>--- a/src/soc/intel/cannonlake/uart.c<br>+++ b/src/soc/intel/cannonlake/uart.c<br>@@ -16,16 +16,19 @@<br> #define __SIMPLE_DEVICE__<br> <br> #include <assert.h><br>+#include <cbmem.h><br> #include <console/uart.h><br>+#include <device/pci.h><br> #include <device/pci_def.h><br> #include <intelblocks/gpio.h><br> #include <intelblocks/lpss.h><br> #include <intelblocks/pcr.h><br> #include <intelblocks/uart.h><br>+#include <soc/iomap.h><br>+#include <soc/nvs.h><br> #include <soc/pch.h><br> #include <soc/pci_devs.h><br> #include <soc/pcr_ids.h><br>-#include <soc/iomap.h><br> <br> /* Serial IO UART controller legacy mode */<br> #define PCR_SERIAL_IO_GPPRVRW7 0x618<br>@@ -48,6 +51,14 @@<br> PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */<br> }<br> };<br>+<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)<br>+uintptr_t uart_platform_base(int idx)<br>+{<br>+ /* We can only have one serial console at a time */<br>+ return UART_BASE_0_ADDR(idx);<br>+}<br>+#endif<br> <br> void pch_uart_init(void)<br> {<br>@@ -75,10 +86,40 @@<br> gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));<br> }<br> <br>-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)<br>-uintptr_t uart_platform_base(int idx)<br>+device_t pch_uart_get_debug_controller(void)<br> {<br>- /* We can only have one serial console at a time */<br>- return UART_BASE_0_ADDR(idx);<br>+ switch (CONFIG_UART_FOR_CONSOLE) {<br>+ case 0:<br>+ return PCH_DEV_UART0;<br>+ case 1:<br>+ return PCH_DEV_UART1;<br>+ case 2:<br>+ default:<br>+ return PCH_DEV_UART2;<br>+ }<br> }<br>-#endif<br>+<br>+void pch_uart_read_resources(struct device *dev)<br>+{<br>+ pci_dev_read_resources(dev);<br>+<br>+ /* Set the configured UART base address for the debug port */<br>+ if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {<br>+ struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>+ /* Need to set the base and size for the resource allocator. */<br>+ res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);<br>+ res->size = UART_DEBUG_BASE_0_SIZE;<br>+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |<br>+ IORESOURCE_FIXED;<br>+ }<br>+}<br>+<br>+bool pch_uart_init_debug_controller_on_resume(void)<br>+{<br>+ global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+<br>+ if (gnvs)<br>+ return !!gnvs->uior;<br>+<br>+ return false;<br>+}<br>diff --git a/src/soc/intel/cannonlake/uart_pch.c b/src/soc/intel/cannonlake/uart_pch.c<br>deleted file mode 100644<br>index 42c7a04..0000000<br>--- a/src/soc/intel/cannonlake/uart_pch.c<br>+++ /dev/null<br>@@ -1,60 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2015 Google Inc.<br>- * Copyright (C) 2017 Intel Corporation<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <cbmem.h><br>-#include <device/pci.h><br>-#include <intelblocks/uart.h><br>-#include <soc/iomap.h><br>-#include <soc/nvs.h><br>-#include <soc/pci_devs.h><br>-<br>-void pch_uart_read_resources(struct device *dev)<br>-{<br>- pci_dev_read_resources(dev);<br>-<br>- /* Set the configured UART base address for the debug port */<br>- if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {<br>- struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- /* Need to set the base and size for the resource allocator. */<br>- res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);<br>- res->size = UART_DEBUG_BASE_0_SIZE;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |<br>- IORESOURCE_FIXED;<br>- }<br>-}<br>-<br>-bool pch_uart_init_debug_controller_on_resume(void)<br>-{<br>- global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>-<br>- if (gnvs)<br>- return !!gnvs->uior;<br>-<br>- return false;<br>-}<br>-<br>-device_t pch_uart_get_debug_controller(void)<br>-{<br>- switch (CONFIG_UART_FOR_CONSOLE) {<br>- case 0:<br>- return PCH_DEV_UART0;<br>- case 1:<br>- return PCH_DEV_UART1;<br>- case 2:<br>- default:<br>- return PCH_DEV_UART2;<br>- }<br>-}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22771">change 22771</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22771"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7eea910e065242689e87adac41281131674b39af </div>
<div style="display:none"> Gerrit-Change-Number: 22771 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>