<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22782">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/cyan: fix FSP memory init params<br><br>In the original Chromium source, PcdMemorySpdPtr is only set for<br>cyan, but none of the other Braswell variants. When upstreamed,<br>it was left set for all boards as it didn't appear to be problematic.<br>In wider testing, I came across one reks board for which it caused<br>FSP memory init to fail, so restricting the paramter to cyan only<br>as it was originally.<br><br>TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM,<br>observe board now successfully boots where it did not previously.<br><br>Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/cyan/romstage.c<br>1 file changed, 5 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22782/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c<br>index c164ea4..5b4bcc0 100644<br>--- a/src/mainboard/google/cyan/romstage.c<br>+++ b/src/mainboard/google/cyan/romstage.c<br>@@ -33,11 +33,13 @@<br>    MEMORY_INIT_UPD *memory_params)<br> {<br>   /* Update SPD data */<br>-        if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN))<br>+    if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {<br>           memory_params->PcdMemoryTypeEnable = MEM_DDR3;<br>-    else<br>+         memory_params->PcdMemorySpdPtr =<br>+                          (u32)params->pei_data->spd_data_ch0;<br>+   } else<br>                memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;<br>-  memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>+<br>     memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>      memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22782">change 22782</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22782"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f </div>
<div style="display:none"> Gerrit-Change-Number: 22782 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>