<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22767">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c<br><br>This patch ensures that all required information for<br>pch/mch/igd deviceid and revision available in single<br>stage and make use of local references.<br><br>TEST=Build and boot soraka/eve<br><br>Change-Id: I420e94043145e8a5adcf8bb51239657891915d84<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/bootblock/report_platform.c<br>M src/soc/intel/cannonlake/include/soc/pch.h<br>2 files changed, 44 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22767/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c<br>index 7bc93e6..9bca7ac 100644<br>--- a/src/soc/intel/cannonlake/bootblock/report_platform.c<br>+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c<br>@@ -46,6 +46,15 @@<br> };<br> <br> static struct {<br>+ u16 lpcid;<br>+ const char *name;<br>+} pch_table[] = {<br>+ { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },<br>+ { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },<br>+ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },<br>+};<br>+<br>+static struct {<br> u16 igdid;<br> const char *name;<br> } igd_table[] = {<br>@@ -58,6 +67,16 @@<br> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },<br> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },<br> };<br>+<br>+static uint8_t get_dev_revision(device_t dev)<br>+{<br>+ return pci_read_config8(dev, PCI_REVISION_ID);<br>+}<br>+<br>+static uint16_t get_dev_id(device_t dev)<br>+{<br>+ return pci_read_config16(dev, PCI_DEVICE_ID);<br>+}<br> <br> static void report_cpu_info(void)<br> {<br>@@ -120,8 +139,9 @@<br> static void report_mch_info(void)<br> {<br> int i;<br>- u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);<br>- u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);<br>+ device_t dev = SA_DEV_ROOT;<br>+ uint16_t mchid = get_dev_id(dev);<br>+ uint8_t mch_revision = get_dev_revision(dev);<br> const char *mch_type = "Unknown";<br> <br> for (i = 0; i < ARRAY_SIZE(mch_table); i++) {<br>@@ -132,13 +152,31 @@<br> }<br> <br> printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",<br>- mchid, mch_revision, mch_type);<br>+ mchid, mch_revision, mch_type);<br>+}<br>+<br>+static void report_pch_info(void)<br>+{<br>+ int i;<br>+ device_t dev = PCH_DEV_LPC;<br>+ uint16_t lpcid = get_dev_id(dev);<br>+ const char *pch_type = "Unknown";<br>+<br>+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {<br>+ if (pch_table[i].lpcid == lpcid) {<br>+ pch_type = pch_table[i].name;<br>+ break;<br>+ }<br>+ }<br>+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",<br>+ lpcid, get_dev_revision(dev), pch_type);<br> }<br> <br> static void report_igd_info(void)<br> {<br> int i;<br>- u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);<br>+ device_t dev = SA_DEV_IGD;<br>+ uint16_t igdid = get_dev_id(dev);<br> const char *igd_type = "Unknown";<br> <br> for (i = 0; i < ARRAY_SIZE(igd_table); i++) {<br>@@ -148,12 +186,13 @@<br> }<br> }<br> printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",<br>- igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);<br>+ igdid, get_dev_revision(dev), igd_type);<br> }<br> <br> void report_platform_info(void)<br> {<br> report_cpu_info();<br> report_mch_info();<br>+ report_pch_info();<br> report_igd_info();<br> }<br>diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h<br>index 7c21dd4..53dd66a 100644<br>--- a/src/soc/intel/cannonlake/include/soc/pch.h<br>+++ b/src/soc/intel/cannonlake/include/soc/pch.h<br>@@ -28,8 +28,6 @@<br> #define PCIE_CLK_LAN 0x70<br> #define PCIE_CLK_FREE 0x80<br> <br>-u8 pch_revision(void);<br>-u16 pch_type(void);<br> void pch_log_state(void);<br> void pch_uart_init(void);<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22767">change 22767</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22767"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 </div>
<div style="display:none"> Gerrit-Change-Number: 22767 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>