<p>Lijian Zhao would like Sathyanarayana Nujella to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22134">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]soc/inte/cannonlake: Add audio NHLT support<br><br>BUG=None<br>TEST=None<br><br>Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/include/soc/nhlt.h<br>A src/soc/intel/cannonlake/nhlt.c<br>4 files changed, 321 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/22134/7</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index f4d524a..ec6284c 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -8,6 +8,7 @@<br> config CPU_SPECIFIC_OPTIONS<br> def_bool y<br> select ACPI_INTEL_HARDWARE_SLEEP_VALUES<br>+ select ACPI_NHLT<br> select ARCH_BOOTBLOCK_X86_32<br> select ARCH_RAMSTAGE_X86_32<br> select ARCH_ROMSTAGE_X86_32<br>@@ -68,6 +69,7 @@<br> select SOC_INTEL_COMMON_BLOCK_SPI<br> select SOC_INTEL_COMMON_BLOCK_TIMER<br> select SOC_INTEL_COMMON_BLOCK_UART<br>+ select SOC_INTEL_COMMON_NHLT<br> select SOC_INTEL_COMMON_SPI_FLASH_PROTECT<br> select SOC_INTEL_COMMON_RESET<br> select SSE2<br>@@ -113,6 +115,41 @@<br> hex<br> default 0x400000<br> <br>+config NHLT_DMIC_1CH_16B<br>+ bool<br>+ depends on ACPI_NHLT<br>+ default n<br>+ help<br>+ Include DSP firmware settings for 1 channel 16B DMIC array.<br>+<br>+config NHLT_DMIC_2CH_16B<br>+ bool<br>+ depends on ACPI_NHLT<br>+ default n<br>+ help<br>+ Include DSP firmware settings for 2 channel 16B DMIC array.<br>+<br>+config NHLT_DMIC_4CH_16B<br>+ bool<br>+ depends on ACPI_NHLT<br>+ default n<br>+ help<br>+ Include DSP firmware settings for 4 channel 16B DMIC array.<br>+<br>+config NHLT_MAX98357<br>+ bool<br>+ depends on ACPI_NHLT<br>+ default n<br>+ help<br>+ Include DSP firmware settings for headset codec.<br>+<br>+config NHLT_DA7219<br>+ bool<br>+ depends on ACPI_NHLT<br>+ default n<br>+ help<br>+ Include DSP firmware settings for headset codec.<br>+<br> config MAX_ROOT_PORTS<br> int<br> default 16<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 076e76b..31dba41 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -40,6 +40,7 @@<br> ramstage-y += i2c.c<br> ramstage-y += lpc.c<br> ramstage-y += memmap.c<br>+ramstage-y += nhlt.c<br> ramstage-y += pmc.c<br> ramstage-y += pmutil.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br>@@ -73,4 +74,32 @@<br> CPPFLAGS_common += -I$(src)/soc/intel/cannonlake<br> CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include<br> <br>+# DSP firmware settings files.<br>+NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cannonlake/nhlt-blobs<br>+DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin<br>+DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin<br>+DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin<br>+MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin<br>+DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin<br>+<br>+cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B)<br>+$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)<br>+$(DMIC_1CH_48KHZ_16B)-type := raw<br>+<br>+cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B)<br>+$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)<br>+$(DMIC_2CH_48KHZ_16B)-type := raw<br>+<br>+cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B)<br>+$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)<br>+$(DMIC_4CH_48KHZ_16B)-type := raw<br>+<br>+cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)<br>+$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)<br>+$(MAX98357_RENDER)-type := raw<br>+<br>+cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)<br>+$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)<br>+$(DA7219_RENDER_CAPTURE)-type := raw<br>+<br> endif<br>diff --git a/src/soc/intel/cannonlake/include/soc/nhlt.h b/src/soc/intel/cannonlake/include/soc/nhlt.h<br>new file mode 100644<br>index 0000000..10de336<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/include/soc/nhlt.h<br>@@ -0,0 +1,43 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SOC_CANNONLAKE_NHLT_H_<br>+#define _SOC_CANNONLAKE_NHLT_H_<br>+<br>+#include <nhlt.h><br>+<br>+#define NHLT_VID 0x8086<br>+#define NHLT_DID_DMIC 0xae20<br>+#define NHLT_DID_BT 0xae30<br>+#define NHLT_DID_SSP 0xae34<br>+<br>+/* The following link values should be used for the hwlink parameters below. */<br>+enum {<br>+ AUDIO_LINK_SSP0,<br>+ AUDIO_LINK_SSP1,<br>+ AUDIO_LINK_SSP2,<br>+ AUDIO_LINK_SSP3,<br>+ AUDIO_LINK_SSP4,<br>+ AUDIO_LINK_SSP5,<br>+ AUDIO_LINK_DMIC,<br>+};<br>+<br>+/* Returns < 0 on error, 0 on success. */<br>+int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels);<br>+int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink);<br>+int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink);<br>+<br>+#endif<br>diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c<br>new file mode 100644<br>index 0000000..9ca54eb<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/nhlt.c<br>@@ -0,0 +1,212 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <nhlt.h><br>+#include <soc/nhlt.h><br>+<br>+static const struct nhlt_format_config dmic_1ch_formats[] = {<br>+ /* 48 KHz 16-bits per sample. */<br>+ {<br>+ .num_channels = 1,<br>+ .sample_freq_khz = 48,<br>+ .container_bits_per_sample = 16,<br>+ .valid_bits_per_sample = 16,<br>+ .settings_file = "dmic-1ch-48khz-16b.bin",<br>+ },<br>+};<br>+<br>+static const struct nhlt_dmic_array_config dmic_1ch_mic_config = {<br>+ .tdm_config = {<br>+ .config_type = NHLT_TDM_MIC_ARRAY,<br>+ },<br>+ .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED,<br>+};<br>+<br>+static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = {<br>+ {<br>+ .link = NHLT_LINK_PDM,<br>+ .device = NHLT_PDM_DEV,<br>+ .direction = NHLT_DIR_CAPTURE,<br>+ .vid = NHLT_VID,<br>+ .did = NHLT_DID_DMIC,<br>+ .cfg = &dmic_1ch_mic_config,<br>+ .cfg_size = sizeof(dmic_1ch_mic_config),<br>+ .formats = dmic_1ch_formats,<br>+ .num_formats = ARRAY_SIZE(dmic_1ch_formats),<br>+ },<br>+};<br>+<br>+static const struct nhlt_format_config dmic_2ch_formats[] = {<br>+ /* 48 KHz 16-bits per sample. */<br>+ {<br>+ .num_channels = 2,<br>+ .sample_freq_khz = 48,<br>+ .container_bits_per_sample = 16,<br>+ .valid_bits_per_sample = 16,<br>+ .settings_file = "dmic-2ch-48khz-16b.bin",<br>+ },<br>+};<br>+<br>+static const struct nhlt_dmic_array_config dmic_2ch_mic_config = {<br>+ .tdm_config = {<br>+ .config_type = NHLT_TDM_MIC_ARRAY,<br>+ },<br>+ .array_type = NHLT_MIC_ARRAY_2CH_SMALL,<br>+};<br>+<br>+static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = {<br>+ {<br>+ .link = NHLT_LINK_PDM,<br>+ .device = NHLT_PDM_DEV,<br>+ .direction = NHLT_DIR_CAPTURE,<br>+ .vid = NHLT_VID,<br>+ .did = NHLT_DID_DMIC,<br>+ .cfg = &dmic_2ch_mic_config,<br>+ .cfg_size = sizeof(dmic_2ch_mic_config),<br>+ .formats = dmic_2ch_formats,<br>+ .num_formats = ARRAY_SIZE(dmic_2ch_formats),<br>+ },<br>+};<br>+<br>+static const struct nhlt_format_config dmic_4ch_formats[] = {<br>+ /* 48 KHz 16-bits per sample. */<br>+ {<br>+ .num_channels = 4,<br>+ .sample_freq_khz = 48,<br>+ .container_bits_per_sample = 16,<br>+ .valid_bits_per_sample = 16,<br>+ .settings_file = "dmic-4ch-48khz-16b.bin",<br>+ },<br>+};<br>+<br>+static const struct nhlt_dmic_array_config dmic_4ch_mic_config = {<br>+ .tdm_config = {<br>+ .config_type = NHLT_TDM_MIC_ARRAY,<br>+ },<br>+ .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED,<br>+};<br>+<br>+static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {<br>+ {<br>+ .link = NHLT_LINK_PDM,<br>+ .device = NHLT_PDM_DEV,<br>+ .direction = NHLT_DIR_CAPTURE,<br>+ .vid = NHLT_VID,<br>+ .did = NHLT_DID_DMIC,<br>+ .cfg = &dmic_4ch_mic_config,<br>+ .cfg_size = sizeof(dmic_4ch_mic_config),<br>+ .formats = dmic_4ch_formats,<br>+ .num_formats = ARRAY_SIZE(dmic_4ch_formats),<br>+ },<br>+};<br>+<br>+static const struct nhlt_format_config da7219_formats[] = {<br>+ /* 48 KHz 24-bits per sample. */<br>+ {<br>+ .num_channels = 2,<br>+ .sample_freq_khz = 48,<br>+ .container_bits_per_sample = 32,<br>+ .valid_bits_per_sample = 24,<br>+ .settings_file = "dialog-2ch-48khz-24b.bin",<br>+ },<br>+};<br>+<br>+static const struct nhlt_tdm_config tdm_config = {<br>+ .virtual_slot = 0,<br>+ .config_type = NHLT_TDM_BASIC,<br>+};<br>+<br>+static const struct nhlt_endp_descriptor da7219_descriptors[] = {<br>+ /* Render Endpoint */<br>+ {<br>+ .link = NHLT_LINK_SSP,<br>+ .device = NHLT_SSP_DEV_I2S,<br>+ .direction = NHLT_DIR_RENDER,<br>+ .vid = NHLT_VID,<br>+ .did = NHLT_DID_SSP,<br>+ .cfg = &tdm_config,<br>+ .cfg_size = sizeof(tdm_config),<br>+ .formats = da7219_formats,<br>+ .num_formats = ARRAY_SIZE(da7219_formats),<br>+ },<br>+ /* Capture Endpoint */<br>+ {<br>+ .link = NHLT_LINK_SSP,<br>+ .device = NHLT_SSP_DEV_I2S,<br>+ .direction = NHLT_DIR_CAPTURE,<br>+ .vid = NHLT_VID,<br>+ .did = NHLT_DID_SSP,<br>+ .cfg = &tdm_config,<br>+ .cfg_size = sizeof(tdm_config),<br>+ .formats = da7219_formats,<br>+ .num_formats = ARRAY_SIZE(da7219_formats),<br>+ },<br>+};<br>+<br>+static const struct nhlt_format_config max98357_formats[] = {<br>+ /* 48 KHz 24-bits per sample. */<br>+ {<br>+ .num_channels = 2,<br>+ .sample_freq_khz = 48,<br>+ .container_bits_per_sample = 32,<br>+ .valid_bits_per_sample = 24,<br>+ .settings_file = "max98357-render-2ch-48khz-24b.bin",<br>+ },<br>+};<br>+<br>+static const struct nhlt_endp_descriptor max98357_descriptors[] = {<br>+ {<br>+ .link = NHLT_LINK_SSP,<br>+ .device = NHLT_SSP_DEV_I2S,<br>+ .direction = NHLT_DIR_RENDER,<br>+ .vid = NHLT_VID,<br>+ .did = NHLT_DID_SSP,<br>+ .formats = max98357_formats,<br>+ .num_formats = ARRAY_SIZE(max98357_formats),<br>+ },<br>+};<br>+<br>+int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels)<br>+{<br>+ switch (num_channels) {<br>+ case 1:<br>+ return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors,<br>+ ARRAY_SIZE(dmic_1ch_descriptors));<br>+ case 2:<br>+ return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors,<br>+ ARRAY_SIZE(dmic_2ch_descriptors));<br>+ case 4:<br>+ return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors,<br>+ ARRAY_SIZE(dmic_4ch_descriptors));<br>+ default:<br>+ return -1;<br>+ }<br>+}<br>+<br>+int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink)<br>+{<br>+ /* Virtual bus id of SSP links are the hardware port ids proper. */<br>+ return nhlt_add_ssp_endpoints(nhlt, hwlink, da7219_descriptors,<br>+ ARRAY_SIZE(da7219_descriptors));<br>+}<br>+<br>+int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink)<br>+{<br>+ /* Virtual bus id of SSP links are the hardware port ids proper. */<br>+ return nhlt_add_ssp_endpoints(nhlt, hwlink, max98357_descriptors,<br>+ ARRAY_SIZE(max98357_descriptors));<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22134">change 22134</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22134"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889 </div>
<div style="display:none"> Gerrit-Change-Number: 22134 </div>
<div style="display:none"> Gerrit-PatchSet: 7 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: AndreX Andraos <andrex.andraos@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> </div>