<p>Lijian Zhao would like Sathyanarayana Nujella to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22144">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[wip]mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219<br><br>Add NHLT and dt support for Audio with Max98357 and DA7219<br><br>TEST=verified NHLT tables and SSDT entries<br>BUG=None<br><br>Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/Kconfig<br>M src/mainboard/intel/cannonlake_rvp/mainboard.c<br>M src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>M src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>M src/soc/intel/cannonlake/chip.h<br>8 files changed, 130 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/22144/12</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig<br>index 1858258..c5eaa8b 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/Kconfig<br>+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig<br>@@ -3,11 +3,15 @@<br> config BOARD_SPECIFIC_OPTIONS<br> def_bool y<br> select BOARD_ROMSIZE_KB_16384<br>- select SOC_INTEL_CANNONLAKE<br>+ select DRIVERS_I2C_GENERIC<br>+ select DRIVERS_GENERIC_MAX98357A<br>+ select DRIVERS_I2C_DA7219<br>+ select GENERIC_SPD_BIN<br> select HAVE_ACPI_RESUME<br> select HAVE_ACPI_TABLES<br> select MAINBOARD_HAS_CHROMEOS<br>- select GENERIC_SPD_BIN<br>+ select SOC_INTEL_CANNONLAKE<br>+ select SND_MAX98357_DA7219<br> <br> config MAINBOARD_DIR<br> string<br>@@ -43,6 +47,13 @@<br> depends on HAVE_IFD_BIN<br> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.bin"<br> <br>+config SND_MAX98357_DA7219<br>+ bool "Include blobs for audio with MAX98357_DA7219"<br>+ select NHLT_DMIC_4CH_16B<br>+ select NHLT_DMIC_2CH_16B<br>+ select NHLT_DA7219<br>+ select NHLT_MAX98357<br>+<br> config ME_BIN_PATH<br> string<br> depends on HAVE_ME_BIN<br>diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c<br>index 855d368..316485d 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/mainboard.c<br>+++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c<br>@@ -13,9 +13,12 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <arch/acpi.h><br> #include <baseboard/variants.h><br> #include <device/device.h><br>+#include <nhlt.h><br> #include <soc/gpio.h><br>+#include <soc/nhlt.h><br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <variant/gpio.h><br> <br>@@ -28,8 +31,33 @@<br> gpio_configure_pads(pads, num);<br> }<br> <br>+static unsigned long mainboard_write_acpi_tables(<br>+ device_t device, unsigned long current, acpi_rsdp_t *rsdp)<br>+{<br>+ uintptr_t start_addr;<br>+ uintptr_t end_addr;<br>+ struct nhlt *nhlt;<br>+<br>+ start_addr = current;<br>+<br>+ nhlt = nhlt_init();<br>+<br>+ if (nhlt == NULL)<br>+ return start_addr;<br>+<br>+ variant_nhlt_init(nhlt);<br>+<br>+ end_addr = nhlt_soc_serialize(nhlt, start_addr);<br>+<br>+ if (end_addr != start_addr)<br>+ acpi_add_table(rsdp, (void *)start_addr);<br>+<br>+ return end_addr;<br>+}<br>+<br> static void mainboard_enable(device_t dev)<br> {<br>+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;<br> dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;<br> }<br> <br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>index 9fb63f5..0ad298b 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>@@ -1,3 +1,4 @@<br> bootblock-y += gpio.c<br> <br> ramstage-y += gpio.c<br>+ramstage-y += nhlt.c<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>index f50c5b7..44632e9 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>@@ -48,8 +48,8 @@<br> PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),<br> /* A19 : ISH_GP_1 */<br> PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),<br>- /* A20 : ISH_GP_2 */<br>- PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1),<br>+ /* A20 : aduio codec irq */<br>+ PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),<br> /* A21 : ISH_GP_3 */<br> PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),<br> /* A22 : ISH_GP_4 */<br>@@ -149,15 +149,19 @@<br> /* D16 : ISH_UART0_CTSB_SML0BALERTB */<br> PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),<br> /* D17 : DMIC_CLK_1_SNDW3_CLK */<br>+ PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),<br> /* D18 : DMIC_DATA_1_SNDW3_DATA */<br>+ PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),<br> /* D19 : DMIC_CLK_0_SNDW4_CLK */<br>+ PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),<br> /* D20 : DMIC_DATA_0_SNDW4_DATA */<br>+ PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),<br> /* D21 : SPI1_IO_2 */<br> PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),<br> /* D22 : SPI1_IO_3 */<br> PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),<br> /* D23 : SPP_MCLK */<br>-<br>+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),<br> /* E0 : SATAXPCIE_0_SATAGP_0 */<br> #if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br> PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),<br>@@ -242,7 +246,9 @@<br> /* H4 : I2C2_SDA */<br> /* H5 : I2C2_SCL */<br> /* H6 : I2C3_SDA */<br>+ PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),<br> /* H7 : I2C3_SCL */<br>+ PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),<br> /* H8 : I2C4_SDA */<br> /* H9 : I2C4_SCL */<br> /* H10 : I2C5_SDA_ISH_I2C2_SDA */<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>index 88d3933..056c57b 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>@@ -28,4 +28,8 @@<br> <br> const struct cros_gpio *variant_cros_gpios(size_t *num);<br> <br>+/* Seed the NHLT tables with the board specific information. */<br>+struct nhlt;<br>+void variant_nhlt_init(struct nhlt *nhlt);<br>+<br> #endif /*__BASEBOARD_VARIANTS_H__ */<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c<br>new file mode 100644<br>index 0000000..e319388<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c<br>@@ -0,0 +1,48 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/variants.h><br>+#include <console/console.h><br>+#include <nhlt.h><br>+#include <soc/nhlt.h><br>+<br>+void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)<br>+{<br>+ /* 1-dmic configuration */<br>+ if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&<br>+ !nhlt_soc_add_dmic_array(nhlt, 1))<br>+ printk(BIOS_ERR, "Added 1CH DMIC array.\n");<br>+ /* 2-dmic configuration */<br>+ if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&<br>+ !nhlt_soc_add_dmic_array(nhlt, 2))<br>+ printk(BIOS_ERR, "Added 2CH DMIC array.\n");<br>+ /* 4-dmic configuration */<br>+ if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&<br>+ !nhlt_soc_add_dmic_array(nhlt, 4))<br>+ printk(BIOS_ERR, "Added 4CH DMIC array.\n");<br>+<br>+#if IS_ENABLED(CONFIG_SND_MAX98357_DA7219)<br>+ /* Dialog for Headset codec.<br>+ * Headset codec is bi-directional but uses the same configuration<br>+ * settings for render and capture endpoints.<br>+ */<br>+ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))<br>+ printk(BIOS_ERR, "Added Dialog_7219 codec.\n");<br>+<br>+ /* MAXIM Smart Amps for left and right speakers. */<br>+ if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1))<br>+ printk(BIOS_ERR, "Added Maxim_98357 codec.\n");<br>+#endif<br>+}<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>index ca46d36..2882182 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -86,7 +86,25 @@<br> device pci 15.0 on end # I2C #0<br> device pci 15.1 on end # I2C #1<br> device pci 15.2 off end # I2C #2<br>- device pci 15.3 off end # I2C #3<br>+ device pci 15.3 on<br>+ chip drivers/i2c/da7219<br>+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)"<br>+ register "btn_cfg" = "50"<br>+ register "mic_det_thr" = "500"<br>+ register "jack_ins_deb" = "20"<br>+ register "jack_det_rate" = ""32ms_64ms""<br>+ register "jack_rem_deb" = "1"<br>+ register "a_d_btn_thr" = "0xa"<br>+ register "d_b_btn_thr" = "0x16"<br>+ register "b_c_btn_thr" = "0x21"<br>+ register "c_mic_btn_thr" = "0x3e"<br>+ register "btn_avg" = "4"<br>+ register "adc_1bit_rpt" = "1"<br>+ register "micbias_lvl" = "2600"<br>+ register "mic_amp_in_sel" = ""diff""<br>+ device i2c 1a on end<br>+ end<br>+ end # I2C #3<br> device pci 16.0 on end # Management Engine Interface 1<br> device pci 16.1 off end # Management Engine Interface 2<br> device pci 16.2 off end # Management Engine IDE-R<br>@@ -122,7 +140,13 @@<br> end # LPC Interface<br> device pci 1f.1 on end # P2SB<br> device pci 1f.2 on end # Power Management Controller<br>- device pci 1f.3 on end # Intel HDA<br>+ device pci 1f.3 on<br>+ chip drivers/generic/max98357a<br>+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"<br>+ register "sdmode_delay" = "5"<br>+ device generic 0 on end<br>+ end<br>+ end # Intel HDA<br> device pci 1f.4 on end # SMBus<br> device pci 1f.5 on end # PCH SPI<br> device pci 1f.6 off end # GbE<br>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>index fd89339..8ee0371 100644<br>--- a/src/soc/intel/cannonlake/chip.h<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -21,6 +21,7 @@<br> #include <intelblocks/gspi.h><br> #include <intelblocks/lpss_i2c.h><br> #include <stdint.h><br>+#include <soc/gpio.h><br> #include <soc/pch.h><br> #include <soc/gpio_defs.h><br> #include <soc/pci_devs.h><br></pre><p>To view, visit <a href="https://review.coreboot.org/22144">change 22144</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22144"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70 </div>
<div style="display:none"> Gerrit-Change-Number: 22144 </div>
<div style="display:none"> Gerrit-PatchSet: 12 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: AndreX Andraos <andrex.andraos@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> </div>