<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22750">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Update PCIe port map<br><br>- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on<br>PCIe port 1, so move the OemCustomize file into the variant directory.<br>- Add comments in baseboard version so it's easier to understand.<br>- Update reset pins, put the definitions in gpio.h<br><br>BUG=b:67309216<br>TEST=Build and boot Kahlee. Build Grunt.<br><br>Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/google/kahlee/Makefile.inc<br>M src/mainboard/google/kahlee/variants/baseboard/Makefile.inc<br>A src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c<br>M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h<br>M src/mainboard/google/kahlee/variants/kahlee/Makefile.inc<br>R src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c<br>M src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h<br>7 files changed, 171 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/22750/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc<br>index 55c80a4..770a999 100644<br>--- a/src/mainboard/google/kahlee/Makefile.inc<br>+++ b/src/mainboard/google/kahlee/Makefile.inc<br>@@ -15,7 +15,6 @@<br> <br> bootblock-y += bootblock/bootblock.c<br> bootblock-y += BiosCallOuts.c<br>-bootblock-y += bootblock/OemCustomize.c<br> bootblock-y += ec.c<br> <br> romstage-y += BiosCallOuts.c<br>diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc<br>index 83eec96..fcaf365 100644<br>--- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc<br>+++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc<br>@@ -14,6 +14,7 @@<br> #<br> <br> bootblock-y += gpio.c<br>+bootblock-y += OemCustomize.c<br> <br> romstage-y += gpio.c<br> romstage-y += memory.c<br>diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c<br>new file mode 100644<br>index 0000000..b46c2da<br>--- /dev/null<br>+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c<br>@@ -0,0 +1,151 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <agesawrapper.h><br>+#include <variant/gpio.h><br>+<br>+static const PCIe_PORT_DESCRIPTOR PortList[] = {<br>+ /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(<br>+ PortDisabled, /* mPortPresent */<br>+ ChannelTypeExt6db, /* mChannelType */<br>+ 2, /* mDevAddress */<br>+ 1, /* mDevFunction */<br>+ HotplugDisabled, /* mHotplug */<br>+ PcieGenMaxSupported, /* mMaxLinkSpeed */<br>+ PcieGenMaxSupported, /* mMaxLinkCap */<br>+ AspmL0sL1, /* mAspm */<br>+ 0, /* mResetId */<br>+ 0) /* mClkPmSupport */<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(<br>+ PortEnabled, /* mPortPresent */<br>+ ChannelTypeExt6db, /* mChannelType */<br>+ 2, /* mDevAddress */<br>+ 2, /* mDevFunction */<br>+ HotplugDisabled, /* mHotplug */<br>+ PcieGenMaxSupported, /* mMaxLinkSpeed */<br>+ PcieGenMaxSupported, /* mMaxLinkCap */<br>+ AspmL0sL1, /* mAspm */<br>+ PCIE_0_RST, /* mResetId */<br>+ 0) /* mClkPmSupport */<br>+ },<br>+ /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(<br>+ PortDisabled, /* mPortPresent */<br>+ ChannelTypeExt6db, /* mChannelType */<br>+ 2, /* mDevAddress */<br>+ 3, /* mDevFunction */<br>+ HotplugDisabled, /* mHotplug */<br>+ PcieGenMaxSupported, /* mMaxLinkSpeed */<br>+ PcieGenMaxSupported, /* mMaxLinkCap */<br>+ AspmL0sL1, /* mAspm */<br>+ PCIE_1_RST, /* mResetId */<br>+ 0) /* mClkPmSupport */<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(<br>+ PortEnabled, /* mPortPresent */<br>+ ChannelTypeExt6db, /* mChannelType */<br>+ 2, /* mDevAddress */<br>+ 4, /* mDevFunction */<br>+ HotplugDisabled, /* mHotplug */<br>+ PcieGenMaxSupported, /* mMaxLinkSpeed */<br>+ PcieGenMaxSupported, /* mMaxLinkCap */<br>+ AspmL0sL1, /* mAspm */<br>+ PCIE_2_RST, /* mResetId */<br>+ 0) /* mClkPmSupport */<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */<br>+ {<br>+ DESCRIPTOR_TERMINATE_LIST,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(<br>+ PortDisabled, /* mPortPresent */<br>+ ChannelTypeExt6db, /* mChannelType */<br>+ 2, /* mDevAddress */<br>+ 5, /* mDevFunction */<br>+ HotplugDisabled, /* mHotplug */<br>+ PcieGenMaxSupported, /* mMaxLinkSpeed */<br>+ PcieGenMaxSupported, /* mMaxLinkCap */<br>+ AspmL0sL1, /* mAspm */<br>+ PCIE_3_RST, /* mResetId */<br>+ 0) /* mClkPmSupport */<br>+ },<br>+};<br>+<br>+static const PCIe_DDI_DESCRIPTOR DdiList[] = {<br>+ /* DDI0 - eDP */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)<br>+ },<br>+ /* DDI1 - DP */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)<br>+ },<br>+ /* DDI2 - DP */<br>+ {<br>+ DESCRIPTOR_TERMINATE_LIST,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)<br>+ },<br>+};<br>+<br>+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {<br>+ .Flags = DESCRIPTOR_TERMINATE_LIST,<br>+ .SocketId = 0,<br>+ .PciePortList = (void *)PortList,<br>+ .DdiLinkList = (void *)DdiList<br>+};<br>+<br>+/*---------------------------------------------------------------------------*/<br>+/**<br>+ * OemCustomizeInitEarly<br>+ *<br>+ * Description:<br>+ * This is the stub function will call the host environment through the<br>+ * binary block interface (call-out port) to provide a user hook opportunity.<br>+ *<br>+ * Parameters:<br>+ * @param[in] **PeiServices<br>+ * @param[in] *InitEarly<br>+ *<br>+ * @retval VOID<br>+ *<br>+ **/<br>+/*---------------------------------------------------------------------------*/<br>+VOID __attribute__((weak)) OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)<br>+{<br>+ InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;<br>+ InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;<br>+ InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;<br>+}<br>diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h<br>index c003673..0ad6740 100644<br>--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h<br>+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h<br>@@ -28,6 +28,12 @@<br> #define CROS_WP_GPIO GPIO_122<br> #define GPIO_EC_IN_RW GPIO_15<br> <br>+/* PCIe reset pins */<br>+#define PCIE_0_RST GPIO_70<br>+#define PCIE_1_RST 0<br>+#define PCIE_2_RST GPIO_26<br>+#define PCIE_3_RST 0<br>+<br> #endif /* _ACPI__ */<br> <br> #define EC_SCI_GPI 22<br>diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc<br>index 83eec96..fcaf365 100644<br>--- a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc<br>+++ b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc<br>@@ -14,6 +14,7 @@<br> #<br> <br> bootblock-y += gpio.c<br>+bootblock-y += OemCustomize.c<br> <br> romstage-y += gpio.c<br> romstage-y += memory.c<br>diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c<br>similarity index 95%<br>rename from src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>rename to src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c<br>index 0551184..7451847 100644<br>--- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>+++ b/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c<br>@@ -14,6 +14,7 @@<br> */<br> <br> #include <agesawrapper.h><br>+#include <variant/gpio.h><br> <br> static const PCIe_PORT_DESCRIPTOR PortList[] = {<br> /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/<br>@@ -25,7 +26,7 @@<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>- AspmL0sL1, 0x04, 0)<br>+ AspmL0sL1, 0, 0)<br> },<br> /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */<br> {<br>@@ -36,7 +37,7 @@<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>- AspmL0sL1, 0x2, 0)<br>+ AspmL0sL1, PCIE_0_RST, 0)<br> },<br> /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */<br> {<br>@@ -47,7 +48,7 @@<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>- AspmL0sL1, 0x3, 0)<br>+ AspmL0sL1, PCIE_1_RST, 0)<br> },<br> /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */<br> {<br>@@ -58,7 +59,7 @@<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>- AspmL0sL1, 0, 0)<br>+ AspmL0sL1, PCIE_2_RST, 0)<br> },<br> /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */<br> {<br>@@ -69,7 +70,7 @@<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>- AspmL0sL1, 0, 0)<br>+ AspmL0sL1, PCIE_3_RST, 0)<br> },<br> };<br> <br>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h<br>index e7097c2..cf62138 100644<br>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h<br>+++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h<br>@@ -32,6 +32,12 @@<br> #define CROS_WP_GPIO GPIO_142<br> #define GPIO_EC_IN_RW GPIO_15<br> <br>+/* PCIe reset pins */<br>+#define PCIE_0_RST GPIO_26<br>+#define PCIE_1_RST GPIO_26<br>+#define PCIE_2_RST 0<br>+#define PCIE_3_RST 0<br>+<br> #endif /* _ACPI__ */<br> <br> /* AGPIO22 -> GPE3 */<br></pre><p>To view, visit <a href="https://review.coreboot.org/22750">change 22750</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22750"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a </div>
<div style="display:none"> Gerrit-Change-Number: 22750 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>