<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22753">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Clean up UART code<br><br>Clean up and move UART related code under a single uart.c file.<br><br>Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/skylake/Makefile.inc<br>D src/soc/intel/skylake/bootblock/uart.c<br>M src/soc/intel/skylake/uart.c<br>D src/soc/intel/skylake/uart_debug.c<br>4 files changed, 54 insertions(+), 94 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/22753/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc<br>index c40f6e1..0e928df 100644<br>--- a/src/soc/intel/skylake/Makefile.inc<br>+++ b/src/soc/intel/skylake/Makefile.inc<br>@@ -14,21 +14,20 @@<br> bootblock-y += i2c.c<br> bootblock-y += bootblock/pch.c<br> bootblock-y += bootblock/report_platform.c<br>-bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c<br>-bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c<br> bootblock-y += gpio.c<br> bootblock-y += gspi.c<br> bootblock-y += pch.c<br> bootblock-y += pmutil.c<br> bootblock-y += spi.c<br> bootblock-y += lpc.c<br>+bootblock-$(CONFIG_UART_DEBUG) += uart.c<br> <br> verstage-y += gspi.c<br> verstage-y += pch.c<br>-verstage-$(CONFIG_UART_DEBUG) += uart_debug.c<br> verstage-y += pmutil.c<br> verstage-y += i2c.c<br> verstage-y += spi.c<br>+verstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br> romstage-y += gpio.c<br> romstage-y += gspi.c<br>@@ -41,7 +40,7 @@<br> romstage-y += pmutil.c<br> romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br> romstage-y += spi.c<br>-romstage-$(CONFIG_UART_DEBUG) += uart_debug.c<br>+romstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c<br>@@ -69,8 +68,7 @@<br> ramstage-y += spi.c<br> ramstage-y += systemagent.c<br> ramstage-y += thermal.c<br>-ramstage-y += uart.c<br>-ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c<br>+ramstage-$(CONFIG_UART_DEBUG) += uart.c<br> ramstage-y += vr_config.c<br> <br> smm-y += elog.c<br>@@ -78,13 +76,12 @@<br> smm-y += pch.c<br> smm-y += pmutil.c<br> smm-y += smihandler.c<br>-smm-$(CONFIG_UART_DEBUG) += uart_debug.c<br>-smm-y += uart.c<br>+smm-$(CONFIG_UART_DEBUG) += uart.c<br> <br> postcar-y += memmap.c<br>-postcar-$(CONFIG_UART_DEBUG) += uart_debug.c<br> postcar-y += gspi.c<br> postcar-y += spi.c<br>+postcar-$(CONFIG_UART_DEBUG) += uart.c<br> <br> # cpu_microcode_bins += ???<br> <br>diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c<br>deleted file mode 100644<br>index f6e7e13..0000000<br>--- a/src/soc/intel/skylake/bootblock/uart.c<br>+++ /dev/null<br>@@ -1,57 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2015 Google Inc.<br>- * Copyright (C) 2015 Intel Corporation<br>- * Copyright (C) 2016 Intel Corporation<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/uart.h><br>-#include <device/pci_def.h><br>-#include <gpio.h><br>-#include <intelblocks/lpss.h><br>-#include <intelblocks/pcr.h><br>-#include <intelblocks/uart.h><br>-#include <soc/bootblock.h><br>-#include <soc/pci_devs.h><br>-#include <soc/pcr_ids.h><br>-<br>-/* Serial IO UART controller legacy mode */<br>-#define PCR_SERIAL_IO_GPPRVRW7 0x618<br>-#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))<br>-<br>-/* UART2 pad configuration. Support RXD and TXD for now. */<br>-static const struct pad_config uart2_pads[] = {<br>-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>-};<br>-<br>-void pch_uart_init(void)<br>-{<br>- uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);<br>-<br>- uart_common_init(PCH_DEV_UART2, base);<br>-<br>- /* Put UART2 in byte access mode for 16550 compatibility */<br>- if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {<br>- pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,<br>- PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));<br>-<br>- /*<br>- * Dummy read after setting any of GPPRVRW7.<br>- * Required for UART 16550 8-bit Legacy mode to become active<br>- */<br>- lpss_clk_read(base);<br>- }<br>-<br>- gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));<br>-}<br>diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c<br>index 3138929..fd4aadc 100644<br>--- a/src/soc/intel/skylake/uart.c<br>+++ b/src/soc/intel/skylake/uart.c<br>@@ -2,7 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2015 Google Inc.<br>- * Copyright (C) 2015 Intel Corporation<br>+ * Copyright (C) 2017 Intel Corporation<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -15,11 +15,57 @@<br> */<br> <br> #include <cbmem.h><br>+#include <console/uart.h><br> #include <device/pci.h><br>+#include <device/pci_def.h><br>+#include <gpio.h><br>+#include <intelblocks/lpss.h><br>+#include <intelblocks/pcr.h><br> #include <intelblocks/uart.h><br>-#include <soc/iomap.h><br>+#include <soc/bootblock.h><br> #include <soc/nvs.h><br> #include <soc/pci_devs.h><br>+#include <soc/pcr_ids.h><br>+<br>+/* Serial IO UART controller legacy mode */<br>+#define PCR_SERIAL_IO_GPPRVRW7 0x618<br>+#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))<br>+<br>+/* UART2 pad configuration. Support RXD and TXD for now. */<br>+static const struct pad_config uart2_pads[] = {<br>+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+};<br>+<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)<br>+uintptr_t uart_platform_base(int idx)<br>+{<br>+ /* Same base address for all debug port usage. In reality UART2<br>+ * is currently only supported. */<br>+ return UART_BASE_0_ADDR(idx);<br>+}<br>+#endif<br>+<br>+void pch_uart_init(void)<br>+{<br>+ uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);<br>+<br>+ uart_common_init(PCH_DEV_UART2, base);<br>+<br>+ /* Put UART2 in byte access mode for 16550 compatibility */<br>+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {<br>+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,<br>+ PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));<br>+<br>+ /*<br>+ * Dummy read after setting any of GPPRVRW7.<br>+ * Required for UART 16550 8-bit Legacy mode to become active<br>+ */<br>+ lpss_clk_read(base);<br>+ }<br>+<br>+ gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));<br>+}<br> <br> #if !ENV_SMM<br> void pch_uart_read_resources(struct device *dev)<br>diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c<br>deleted file mode 100644<br>index eedf656..0000000<br>--- a/src/soc/intel/skylake/uart_debug.c<br>+++ /dev/null<br>@@ -1,26 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright 2015 Google Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stddef.h><br>-#include <console/uart.h><br>-#include <soc/iomap.h><br>-#include <soc/serialio.h><br>-<br>-uintptr_t uart_platform_base(int idx)<br>-{<br>- /* Same base address for all debug port usage. In reality UART2<br>- * is currently only supported. */<br>- return UART_BASE_0_ADDR(idx);<br>-}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22753">change 22753</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22753"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed </div>
<div style="display:none"> Gerrit-Change-Number: 22753 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>