<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22755">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Remove pch_enable_dev() from SoC<br><br>PCI resources MMIO space/bus master enabling handles inside<br>pch_dev_enable_resources() from common device code. Hence<br>no need to have an explicit soc function to do the same.<br><br>TEST=lspci from kernel console shows same pci device list<br>without and without this patch.<br><br>Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip_fsp20.c<br>M src/soc/intel/skylake/pch.c<br>3 files changed, 4 insertions(+), 52 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/22755/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c<br>index dfa813a..3e33053 100644<br>--- a/src/soc/intel/skylake/chip.c<br>+++ b/src/soc/intel/skylake/chip.c<br>@@ -63,17 +63,10 @@<br> static void soc_enable(device_t dev)<br> {<br> /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>+ if (dev->path.type == DEVICE_PATH_DOMAIN)<br> dev->ops = &pci_domain_ops;<br>- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)<br> dev->ops = &cpu_bus_ops;<br>- } else if (dev->path.type == DEVICE_PATH_PCI) {<br>- /* Handle PCH device enable */<br>- if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&<br>- (dev->ops == NULL || dev->ops->enable == NULL)) {<br>- pch_enable_dev(dev);<br>- }<br>- }<br> }<br> <br> struct chip_operations soc_intel_skylake_ops = {<br>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c<br>index bc0f5a5..8e5cc2a 100644<br>--- a/src/soc/intel/skylake/chip_fsp20.c<br>+++ b/src/soc/intel/skylake/chip_fsp20.c<br>@@ -74,17 +74,10 @@<br> static void soc_enable(device_t dev)<br> {<br> /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>+ if (dev->path.type == DEVICE_PATH_DOMAIN)<br> dev->ops = &pci_domain_ops;<br>- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)<br> dev->ops = &cpu_bus_ops;<br>- } else if (dev->path.type == DEVICE_PATH_PCI) {<br>- /* Handle PCH device enable */<br>- if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&<br>- (dev->ops == NULL || dev->ops->enable == NULL)) {<br>- pch_enable_dev(dev);<br>- }<br>- }<br> }<br> <br> struct chip_operations soc_intel_skylake_ops = {<br>diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c<br>index 7084fa2..451bebb 100644<br>--- a/src/soc/intel/skylake/pch.c<br>+++ b/src/soc/intel/skylake/pch.c<br>@@ -16,14 +16,10 @@<br> */<br> <br> #include <arch/io.h><br>-#include <console/console.h><br>-#include <delay.h><br> #include <device/device.h><br> #include <device/pci.h><br>-#include <device/pci_def.h><br> #include <soc/pch.h><br> #include <soc/pci_devs.h><br>-#include <soc/ramstage.h><br> <br> u8 pch_revision(void)<br> {<br>@@ -34,33 +30,3 @@<br> {<br> return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);<br> }<br>-<br>-#if ENV_RAMSTAGE<br>-void pch_enable_dev(device_t dev)<br>-{<br>- /* FSP should implement routines to disable PCH IPs */<br>- u32 reg32;<br>-<br>- /* These devices need special enable/disable handling */<br>- switch (PCI_SLOT(dev->path.pci.devfn)) {<br>- case PCH_DEV_SLOT_PCIE:<br>- return;<br>- }<br>-<br>- if (!dev->enabled) {<br>- printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));<br>-<br>- /* Ensure memory, io, and bus master are all disabled */<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 &= ~(PCI_COMMAND_MASTER |<br>- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>- } else {<br>- /* Enable SERR */<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 |= PCI_COMMAND_SERR;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>- }<br>-}<br>-<br>-#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22755">change 22755</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22755"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1 </div>
<div style="display:none"> Gerrit-Change-Number: 22755 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>