<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22687">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/i440bx: Correct RAM init programming<br><br>Corrects MBSC/MBFS programming when initializing DRAM on boards with both<br>3 and 4 DIMM slots.<br><br>Reformats comments to current coreboot standards.<br><br>Drops some romcc "optimizations" no longer necessary.<br><br>Boot tested on asus/p2b-ls, where it fixes a memory related hang after<br>SeaBIOS resets the board with nothing to boot from.<br><br>Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/northbridge/intel/i440bx/raminit.c<br>1 file changed, 149 insertions(+), 79 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22687/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c<br>index 84008e7..439fb14 100644<br>--- a/src/northbridge/intel/i440bx/raminit.c<br>+++ b/src/northbridge/intel/i440bx/raminit.c<br>@@ -431,40 +431,43 @@<br> <br> static void set_dram_buffer_strength(void)<br> {<br>- /* To give some breathing room for romcc,<br>- * mbsc0 doubles as drb<br>- * mbsc1 doubles as drb1<br>- * mbfs0 doubles as i and reg<br>+ /*<br>+ * Program MBSC[39:0] and MBFS[23:0].<br>+ *<br>+ * The 440BX datasheet says buffer frequency is independent from bus<br>+ * frequency and mismatch both ways are possible.<br>+ *<br>+ * MBSC[47:40] and MBFS[23] are reserved.<br> */<br>- uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb;<br> <br>- /* Tally how many rows between rows 0-3 and rows 4-7 are populated.<br>+ unsigned int i, reg, drb;<br>+ uint8_t mbsc0, mbsc1, mbsc2, mbsc3, mbsc4, mbfs0, mbfs1, mbfs2;<br>+<br>+ /*<br>+ * Tally how many rows between rows 0-3 and rows 4-7 are populated.<br> * This determines how to program MBFS and MBSC.<br> */<br> uint8_t dimm03 = 0;<br> uint8_t dimm47 = 0;<br> <br>- mbsc0 = 0;<br>- for (mbfs0 = DRB0; mbfs0 <= DRB7; mbfs0++) {<br>- mbsc1 = pci_read_config8(NB, mbfs0);<br>- if (mbsc0 != mbsc1) {<br>- if (mbfs0 <= DRB3) {<br>+ for (drb = 0, i = DRB0; i <= DRB7; i++) {<br>+ reg = pci_read_config8(NB, i);<br>+ if (drb != reg) {<br>+ if (i <= DRB3)<br> dimm03++;<br>- } else {<br>+ else<br> dimm47++;<br>- }<br>- mbsc0 = mbsc1;<br>+<br>+ drb = reg;<br> }<br> }<br> <br>- /* Algorithm bitmap for programming MBSC[39:0] and MBFS[23:0].<br>+ #if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)<br>+ /*<br>+ * For a 4 DIMM board, based on ASUS P2B-LS mainboard.<br> *<br>- * The 440BX datasheet says buffer frequency is independent from bus<br>- * frequency and mismatch both ways are possible. This is how it is<br>- * programmed in the ASUS P2B-LS mainboard.<br>- *<br>- * There are four main conditions to check when programming DRAM buffer<br>- * frequency and strength:<br>+ * There are four main conditions to check when programming<br>+ * DRAM buffer frequency and strength:<br> *<br> * a: >2 rows populated across DIMM0,1<br> * b: >2 rows populated across DIMM2,3<br>@@ -474,62 +477,56 @@<br> * 6: NBXCFG[13] strapped as 66MHz<br> *<br> * CKE0/FENA ----------------------------------------------------------+<br>- * CKE1/GCKE -------------------[ MBFS ]------------------------+|<br>- * DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+||<br>- * DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+|||<br>- * DQMB5/CASB5# ---------------------------------------------------+||||<br>- * DQMA1/CASA1# --------------------------------------------------+|||||<br>- * DQMA5/CASA5# -------------------------------------------------+||||||<br>- * CSA0-5#,CSB0-5# ----------------------------------------++++++|||||||<br>- * CSA6#/CKE2# -------------------------------------------+|||||||||||||<br>- * CSB6#/CKE4# ------------------------------------------+||||||||||||||<br>- * CSA7#/CKE3# -----------------------------------------+|||||||||||||||<br>- * CSB7#/CKE5# ----------------------------------------+||||||||||||||||<br>- * MECC[7:0] #2/#1 (100MHz) -------------------------++|||||||||||||||||<br>- * MD[63:0] #2/#1 (100MHz) ------------------------++|||||||||||||||||||<br>+ * CKE1/GCKE ----------------------[ MBFS ]---------------------+|<br>+ * DQMA/CASA[764320]# -------------[ 0 = 66MHz ]--------------------+||<br>+ * DQMB1/CASB1# (Fixed for 66MHz) -[ 1 = 100MHz ]-------------------+|||<br>+ * DQMB5/CASB5# (Fixed for 66MHz) ---------------------------------+||||<br>+ * DQMA1/CASA1# (Fixed for 66MHz) --------------------------------+|||||<br>+ * DQMA5/CASA5# (Fixed for 66MHz) -------------------------------+||||||<br>+ * CSA[5:0]#,CSB[5:0]# ------------------------------------++++++|||||||<br>+ * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||<br>+ * MECC[7:0] #2/#1 ----------------------------------++|||||||||||||||||<br>+ * MD[63:0] #2/#1 ---------------------------------++|||||||||||||||||||<br> * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||<br> * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||<br> * Reserved ------------------------------------+|||||||||||||||||||||||<br> * ||||||||||||||||||||||||<br>- * 3 32 21 10 0 * 2 21 10 0<br>- * 9876543210987654321098765432109876543210 * 321098765432109876543210<br>- * a 10------------------------1010---------- * -1---------------11----- a<br>- *!a 11------------------------1111---------- * -0---------------00----- !a<br>- * b --10--------------------------1010------ * --1----------------11--- b<br>- *!b --11--------------------------1111------ * --0----------------00--- !b<br>- * c ----------------------------------1100-- * ----------------------1- c<br>- *!c ----------------------------------1011-- * ----------------------0- !c<br>- * 1 ----1010101000000000000000------------00 * ---11111111111111----1-0 1<br>- * 6 ----000000000000000000000010101010----00 * ---1111111111111100000-0 6<br>- * | | | | | | | | | | ||||||| | | | | | |<br>- * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA<br>- * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE<br>- * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#<br>- * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1#<br>- * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5#<br>- * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1#<br>- * | | | | | | | | | | ||||||+------------- DQMA5/CASA5#<br>- * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# [ 0=1x;1=2x ]<br>- * | | | | | | | | | +--------------------- CSA6#/CKE2#<br>- * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4#<br>- * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3#<br>- * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5#<br>- * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (2x)<br>- * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (2x)<br>- * | | | +--------------------------------- MD[63:0] #1 (2x)<br>- * | | +----------------------------------- MD[63:0] #2 (2x)<br>- * | +------------------------------------- MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#<br>- * +--------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#<br>- * MBSC[47:40] and MBFS[23] are reserved.<br>- *<br>- * This algorithm is checked against the ASUS P2B-LS (which has<br>- * 4 DIMM slots) factory BIOS.<br>- * Therefore it assumes a board with 4 slots, and will need testing<br>- * on boards with 3 DIMM slots.<br>+ * 3 32 21 10 0 * 2 21 10 0<br>+ * 9876543210987654321098765432109876543210 * 321098765432109876543210<br>+ * 10------------------------1010---------- a -1---------------11-----<br>+ * 11------------------------1111---------- !a -0---------------00-----<br>+ * --10--------------------------1010------ b --1----------------11---<br>+ * --11--------------------------1111------ !b --0----------------00---<br>+ * ----------------------------------1100-- c ----------------------1-<br>+ * ----------------------------------1011-- !c ----------------------0-<br>+ * ----1010101000000000000000------------00 1 ---11111111111111----1-0<br>+ * ----000000000000000000000010101010----00 6 ---1111111111111100000-0<br>+ * | | | | | | | | | | ||||||| | | | | | |<br>+ * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA<br>+ * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE<br>+ * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#<br>+ * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# (66MHz: 2x)<br>+ * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# (66MHz: 2x)<br>+ * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# (66MHz: 2x)<br>+ * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# (66MHz: 2x)<br>+ * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (1x)<br>+ * | | | | | | | | | +--------------------- CSA6#/CKE2<br>+ * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4<br>+ * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3<br>+ * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5<br>+ * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1<br>+ * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2<br>+ * | | | +--------------------------------- MD[63:0] #1<br>+ * | | +----------------------------------- MD[63:0] #2<br>+ * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#<br>+ * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#<br> */<br>+ unsigned int fsb;<br> <br> mbsc0 = 0x80;<br> mbsc1 = 0x2a;<br>+ mbsc2 = 0;<br>+ mbfs1 = 0xff;<br> mbfs2 = 0x1f;<br> if (pci_read_config8(NB, NBXCFG + 1) & 0x30) {<br> fsb = 66;<br>@@ -542,24 +539,21 @@<br> mbsc4 = 0x0a;<br> mbfs0 = 0x84;<br> }<br>-<br> if (dimm03 > 2) {<br> mbsc4 = mbsc4 | 0x80;<br>- mbsc1 = mbsc1 | 0x28;<br> mbfs2 = mbfs2 | 0x40;<br>- mbfs0 = mbfs0 | 0x60;<br>+ if (fsb == 100)<br>+ mbfs0 |= 0x60;<br> } else {<br> mbsc4 = mbsc4 | 0xc0;<br>- if (fsb == 100) {<br>+ if (fsb == 100)<br> mbsc1 = mbsc1 | 0x3c;<br>- }<br> }<br> if (dimm47 > 2) {<br> mbsc4 = mbsc4 | 0x20;<br>- mbsc1 = mbsc1 | 0x02;<br>- mbsc0 = mbsc0 | 0x80;<br> mbfs2 = mbfs2 | 0x20;<br>- mbfs0 = mbfs0 | 0x18;<br>+ if (fsb == 100)<br>+ mbfs0 |= 0x18;<br> } else {<br> mbsc4 = mbsc4 | 0x30;<br> if (fsb == 100) {<br>@@ -573,14 +567,90 @@<br> } else {<br> mbsc0 = mbsc0 | 0x2c;<br> }<br>+ #else<br>+ /*<br>+ * For a 3 DIMM board, based on ASUS P2B mainboard.<br>+ *<br>+ * There are two main conditions to check when programming DRAM buffer<br>+ * frequency and strength:<br>+ *<br>+ * a: >2 rows populated across DIMM0,1<br>+ * c: >4 rows populated across all DIMM slots<br>+ *<br>+ * CKE0 ---------------------------------------------------------------+<br>+ * CKE1 ------------------------[ MBFS ]------------------------+|<br>+ * DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+||<br>+ * DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+|||<br>+ * DQMB5/CASB5# ---------------------------------------------------+||||<br>+ * DQMA1/CASA1# --------------------------------------------------+|||||<br>+ * DQMA5/CASA5# -------------------------------------------------+||||||<br>+ * CSA0-5#,CSB0-5# ----------------------------------------++++++|||||||<br>+ * CSA6#/CKE2 --------------------------------------------+|||||||||||||<br>+ * CSB6#/CKE4 -------------------------------------------+||||||||||||||<br>+ * CSA7#/CKE3 ------------------------------------------+|||||||||||||||<br>+ * CSB7#/CKE5 -----------------------------------------+||||||||||||||||<br>+ * MECC[7:0] #2/#1 (100MHz) -------------------------++|||||||||||||||||<br>+ * MD[63:0] #2/#1 (100MHz) ------------------------++|||||||||||||||||||<br>+ * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||<br>+ * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||<br>+ * Reserved ------------------------------------+|||||||||||||||||||||||<br>+ * ||||||||||||||||||||||||<br>+ * 3 32 21 10 0 * 2 21 10 0<br>+ * 9876543210987654321098765432109876543210 * 321098765432109876543210<br>+ * 10------------------------1111---------- a -1----------------------<br>+ * 11------------------------1010---------- !a -0----------------------<br>+ * --110000000010101010111111----1010--1010 * --01111000000000000000-0<br>+ * ----------------------------------11---- c ----------------------1-<br>+ * ----------------------------------10---- !c ----------------------0-<br>+ * | | | | | | | | | | ||||||| | | | | | |<br>+ * | | | | | | | | | | ||||||| | | | | | +- CKE0<br>+ * | | | | | | | | | | ||||||| | | | | +--- CKE1<br>+ * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#<br>+ * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1#<br>+ * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5#<br>+ * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1#<br>+ * | | | | | | | | | | ||||||+------------- DQMA5/CASA5#<br>+ * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (2x)<br>+ * | | | | | | | | | +--------------------- CSA6#/CKE2<br>+ * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4<br>+ * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3<br>+ * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5<br>+ * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (1x)<br>+ * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (1x)<br>+ * | | | +--------------------------------- MD[63:0] #1 (1x)<br>+ * | | +----------------------------------- MD[63:0] #2 (1x)<br>+ * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#<br>+ * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#<br>+ */<br>+<br>+ mbsc0 = 0xaa;<br>+ mbsc1 = 0xea;<br>+ mbsc2 = 0xaf;<br>+ mbsc3 = 0x0a;<br>+ mbsc4 = 0xb0;<br>+ mbfs0 = 0x00;<br>+ mbfs1 = 0x00;<br>+ mbfs2 = 0x1e;<br>+<br>+ if (dimm03 > 2) {<br>+ mbfs2 |= 0x40;<br>+ } else {<br>+ mbsc4 |= 0xc0;<br>+ mbsc1 |= 0x3c;<br>+ }<br>+ if ((dimm03 + dimm47) > 4) {<br>+ mbsc0 |= 0x30;<br>+ mbfs0 |= 0x02;<br>+ }<br>+ #endif<br> <br> pci_write_config8(NB, MBSC + 0, mbsc0);<br> pci_write_config8(NB, MBSC + 1, mbsc1);<br>- pci_write_config8(NB, MBSC + 2, 0x00);<br>+ pci_write_config8(NB, MBSC + 2, mbsc2);<br> pci_write_config8(NB, MBSC + 3, mbsc3);<br> pci_write_config8(NB, MBSC + 4, mbsc4);<br> pci_write_config8(NB, MBFS + 0, mbfs0);<br>- pci_write_config8(NB, MBFS + 1, 0xff);<br>+ pci_write_config8(NB, MBFS + 1, mbfs1);<br> pci_write_config8(NB, MBFS + 2, mbfs2);<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22687">change 22687</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22687"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0 </div>
<div style="display:none"> Gerrit-Change-Number: 22687 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>