<p>Tobias Diedrich has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22683">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/dcp847ske: Add Intel NUC DCP847SKE<br><br>https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE<br><br>Tested:<br>- RAM slots with 2x4GB Kingston KVR1333D3S9/4G<br>- SeaBIOS payload<br>- Linux payload<br>- Booting into Linux 4.13.14 with Debian/unstable installed on the<br> internal mSATA slot.<br>- Non-native raminit (works)<br>- Native raminit (doesn't work with the given ram)<br>- Native VGA init, HDMI port detection with libgfxinit<br>- Basic ACPI functions (power button event; power-off; reboot)<br>- Suspend to RAM and resume works<br>- PCIe WLAN in half-minicard slot<br>- USB device in half-minicard slot<br>- PCIe device in full-minicard slot<br>- mSATA device in full-minicard slot<br>- Fan spins up/down in response to CPU load<br><br>Known issues:<br>- Native raminit fails timC calibration with the RAM I have<br>- Technical Product Specification mentions overcurrent protection<br> for back panel and front panel USB connectors, but I haven't<br> been able to trigger it with either native fw or coreboot<br> (tried up to 2.5A load).<br><br>Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90<br>Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>---<br>A src/mainboard/intel/dcp847ske/Kconfig<br>A src/mainboard/intel/dcp847ske/Kconfig.name<br>A src/mainboard/intel/dcp847ske/Makefile.inc<br>A src/mainboard/intel/dcp847ske/acpi/ec.asl<br>A src/mainboard/intel/dcp847ske/acpi/platform.asl<br>A src/mainboard/intel/dcp847ske/acpi/superio.asl<br>A src/mainboard/intel/dcp847ske/acpi_tables.c<br>A src/mainboard/intel/dcp847ske/board_info.txt<br>A src/mainboard/intel/dcp847ske/devicetree.cb<br>A src/mainboard/intel/dcp847ske/dsdt.asl<br>A src/mainboard/intel/dcp847ske/early_southbridge.c<br>A src/mainboard/intel/dcp847ske/gma-mainboard.ads<br>A src/mainboard/intel/dcp847ske/gnvs.c<br>A src/mainboard/intel/dcp847ske/gpio.c<br>A src/mainboard/intel/dcp847ske/hda_verb.c<br>A src/mainboard/intel/dcp847ske/mainboard.c<br>A src/mainboard/intel/dcp847ske/romstage.c<br>A src/mainboard/intel/dcp847ske/smihandler.c<br>A src/mainboard/intel/dcp847ske/superio.h<br>A src/mainboard/intel/dcp847ske/thermal.h<br>A src/mainboard/intel/dcp847ske/usb.h<br>A src/southbridge/intel/bd82x6x/acpi/gbe.asl<br>M src/southbridge/intel/bd82x6x/acpi/pch.asl<br>23 files changed, 1,076 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/22683/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig<br>new file mode 100644<br>index 0000000..6c99bc4<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/Kconfig<br>@@ -0,0 +1,94 @@<br>+if BOARD_INTEL_DCP847SKE<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select BOARD_ROMSIZE_KB_8192<br>+ select CPU_INTEL_SOCKET_RPGA989<br>+ select HAVE_ACPI_RESUME<br>+ select HAVE_ACPI_TABLES<br>+ select NORTHBRIDGE_INTEL_SANDYBRIDGE<br>+ select SOUTHBRIDGE_INTEL_C216<br>+ select SERIRQ_CONTINUOUS_MODE<br>+ select INTEL_INT15<br>+ select MAINBOARD_HAS_LIBGFXINIT<br>+<br>+menu "Debugging"<br>+<br>+config ENABLE_UART_ON_TESTPADS<br>+ bool "Enable UART on testpads"<br>+ default n<br>+ help<br>+ Serial output requires soldering to the testpad next to<br>+ NCT5577D pin 18 (txd) and gnd.<br>+<br>+endmenu<br>+<br>+config NO_UART_ON_SUPERIO<br>+ def_bool y<br>+ depends on !ENABLE_UART_ON_TESTPADS<br>+<br>+config HAVE_IFD_BIN<br>+ bool<br>+ default n<br>+<br>+config HAVE_ME_BIN<br>+ bool<br>+ default n<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default intel/dcp847ske<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "Intel NUC DCP847SKE"<br>+<br>+config VGA_BIOS_FILE<br>+ string<br>+ default "pci8086,0106.rom"<br>+<br>+config VGA_BIOS_ID<br>+ string<br>+ default "8086,0106"<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>+ hex<br>+ default 0x2044<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>+ hex<br>+ default 0x8086<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 2<br>+<br>+config USBDEBUG_HCD_INDEX<br>+ int<br>+ default 2<br>+<br>+config IFD_GBE_SECTION<br>+ string<br>+ default "0x00001000:0x00002fff"<br>+<br>+config IFD_ME_SECTION<br>+ string<br>+ default "0x00003000:0x001bffff"<br>+<br>+config IFD_BIOS_SECTION<br>+ string<br>+ default "0x001c0000:0x007fffff"<br>+<br>+config CBFS_SIZE<br>+ hex<br>+ default 0x00640000<br>+<br>+config MAINBOARD_SMBIOS_MANUFACTURER<br>+ string<br>+ default "Intel Corporation"<br>+<br>+config MAINBOARD_SMBIOS_PRODUCT_NAME<br>+ string<br>+ default "DCP847SKE"<br>+<br>+endif # BOARD_INTEL_DCP847SKE<br>diff --git a/src/mainboard/intel/dcp847ske/Kconfig.name b/src/mainboard/intel/dcp847ske/Kconfig.name<br>new file mode 100644<br>index 0000000..e55b90d<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_INTEL_DCP847SKE<br>+ bool "Intel NUC DCP847SKE"<br>diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc<br>new file mode 100644<br>index 0000000..4435806<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/Makefile.inc<br>@@ -0,0 +1,5 @@<br>+romstage-y += early_southbridge.c<br>+romstage-y += gpio.c<br>+ramstage-y += gnvs.c<br>+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads<br>+smm-y += smihandler.c<br>diff --git a/src/mainboard/intel/dcp847ske/acpi/ec.asl b/src/mainboard/intel/dcp847ske/acpi/ec.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/acpi/ec.asl<br>diff --git a/src/mainboard/intel/dcp847ske/acpi/platform.asl b/src/mainboard/intel/dcp847ske/acpi/platform.asl<br>new file mode 100644<br>index 0000000..ff5b176<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/acpi/platform.asl<br>@@ -0,0 +1,29 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * The _PTS method (Prepare To Sleep) is called before the OS is<br>+ * entering a sleep state. The sleep state number is passed in Arg0<br>+ */<br>+Method(_WAK,1)<br>+{<br>+ Return(Package(){0,0})<br>+}<br>+<br>+/* The _WAK method is called on system wakeup */<br>+Method(_PTS,1)<br>+{<br>+}<br>diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl<br>diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c<br>new file mode 100644<br>index 0000000..2997587<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/acpi_tables.c<br>@@ -0,0 +1 @@<br>+/* dummy */<br>diff --git a/src/mainboard/intel/dcp847ske/board_info.txt b/src/mainboard/intel/dcp847ske/board_info.txt<br>new file mode 100644<br>index 0000000..32d4eba<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Category: desktop<br>+ROM package: SOIC-8<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>+Release year: 2013<br>diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb<br>new file mode 100644<br>index 0000000..6bc2ed5<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/devicetree.cb<br>@@ -0,0 +1,67 @@<br>+chip northbridge/intel/sandybridge<br>+ # IGD Displays<br>+ register "gfx.ndid" = "3"<br>+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"<br>+<br>+ # Enable DisplayPort 1 Hotplug with 6ms pulse<br>+ register "gpu_dp_d_hotplug" = "0x06"<br>+<br>+ # Enable DisplayPort 0 Hotplug with 6ms pulse<br>+ register "gpu_dp_c_hotplug" = "0x06"<br>+<br>+ # Enable DVI Hotplug with 6ms pulse<br>+ register "gpu_dp_b_hotplug" = "0x06"<br>+<br>+ device cpu_cluster 0x0 on<br>+ chip cpu/intel/socket_rPGA989<br>+ device lapic 0x0 on end<br>+ end<br>+ chip cpu/intel/model_206ax<br>+ # Magic APIC ID to locate this chip<br>+ device lapic 0xACAC off end<br>+<br>+ register "c1_battery" = "1"<br>+ register "c2_battery" = "3"<br>+ register "c3_battery" = "5"<br>+<br>+ register "c1_acpower" = "1"<br>+ register "c2_acpower" = "3"<br>+ register "c3_acpower" = "5"<br>+ end<br>+ end<br>+ device domain 0x0 on<br>+ device pci 00.0 on end # Host bridge Host bridge<br>+ device pci 01.0 off end # PCIe Bridge for discrete graphics<br>+ device pci 02.0 on end # Internal graphics VGA controller<br>+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH<br>+ register "c2_latency" = "0x0065"<br>+ register "sata_port_map" = "0x1"<br>+ register "spi_lvscc" = "0x2005"<br>+ register "spi_uvscc" = "0x2005"<br>+<br>+ register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff<br>+<br>+ device pci 16.0 on end # Management Engine Interface 1<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT<br>+ device pci 19.0 on end # Intel Gigabit Ethernet<br>+ device pci 1b.0 on end # High Definition Audio Audio controller<br>+ device pci 1c.0 on end # PCIe Port #1 (unused)<br>+ device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA)<br>+ device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe)<br>+ device pci 1c.3 off end # PCIe Port #4<br>+ device pci 1c.4 off end # PCIe Port #5<br>+ device pci 1c.5 off end # PCIe Port #6<br>+ device pci 1c.6 off end # PCIe Port #7<br>+ device pci 1c.7 off end # PCIe Port #8<br>+ device pci 1d.0 on end # USB2 EHCI #1<br>+ device pci 1e.0 off end # PCI bridge<br>+ device pci 1f.0 on end # LPC bridge PCI-LPC bridge<br>+ device pci 1f.2 on end # SATA Controller 1<br>+ device pci 1f.3 on end # SMBus<br>+ device pci 1f.5 off end # SATA Controller 2<br>+ device pci 1f.6 off end # Thermal<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl<br>new file mode 100644<br>index 0000000..f637648<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/dsdt.asl<br>@@ -0,0 +1,43 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x03, // DSDT revision: ACPI v3.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20141018 // OEM revision<br>+)<br>+{<br>+ // Some generic macros<br>+ #include "acpi/platform.asl"<br>+ #include <cpu/intel/model_206ax/acpi/cpu.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/platform.asl><br>+ /* global NVS and variables. */<br>+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl><br>+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/pch.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl><br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c<br>new file mode 100644<br>index 0000000..9dcba5d<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c<br>@@ -0,0 +1,199 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <string.h><br>+#include <lib.h><br>+#include <timestamp.h><br>+#include <arch/byteorder.h><br>+#include <arch/io.h><br>+#include <device/pci_def.h><br>+#include <device/pnp_def.h><br>+#include <cpu/x86/lapic.h><br>+#include <arch/acpi.h><br>+#include <console/console.h><br>+#include "northbridge/intel/sandybridge/sandybridge.h"<br>+#include "northbridge/intel/sandybridge/raminit_native.h"<br>+#include "southbridge/intel/bd82x6x/pch.h"<br>+#include <southbridge/intel/common/gpio.h><br>+#include <arch/cpu.h><br>+#include <cpu/x86/msr.h><br>+<br>+#include "superio.h"<br>+#include "thermal.h"<br>+<br>+#if IS_ENABLED(CONFIG_ENABLE_UART_ON_TESTPADS)<br>+#define DEBUG_UART_EN COMA_LPC_EN<br>+#else<br>+#define DEBUG_UART_EN 0<br>+#endif<br>+<br>+void pch_enable_lpc(void)<br>+{<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,<br>+ CNF2_LPC_EN | DEBUG_UART_EN);<br>+ /* Decode SuperIO 0x0a00 */<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);<br>+}<br>+<br>+void rcba_config(void)<br>+{<br>+ /* Disable devices */<br>+ RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI;<br>+<br>+#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)<br>+ /* Enable Gigabit Ethernet */<br>+ if (RCBA32(BUC) & PCH_DISABLE_GBE) {<br>+ RCBA32(BUC) &= ~PCH_DISABLE_GBE;<br>+ /* Datasheet says clearing the bit requires a reset after */<br>+ printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");<br>+ outb(0xe, 0xcf9);<br>+ halt();<br>+ }<br>+#endif<br>+<br>+ /* Set "mobile" bit in MCH (which makes sense layout-wise). */<br>+ /* Note sure if this has any effect at all though. */<br>+ MCHBAR32(0x0004) |= 0x00001000;<br>+ MCHBAR32(0x0104) |= 0x00001000;<br>+}<br>+<br>+void mainboard_early_init(int s3resume)<br>+{<br>+}<br>+<br>+static const u16 hwm_initvals[] = {<br>+ HWM_BANK(0),<br>+ HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */<br>+<br>+ HWM_BANK(7), /* PECI */<br>+ HWM_INITVAL(0x01, 0x95), /* Enable PECI */<br>+ HWM_INITVAL(0x03, 0x10), /* Enable Agent 0 */<br>+ HWM_INITVAL(0x09, 0x64), /* Tbase0 */<br>+<br>+ HWM_BANK(2), /* CPUFAN control */<br>+ HWM_INITVAL(0x00, 0x0c), /* PECI Agent 0 as CPUFAN monitoring source */<br>+ HWM_INITVAL(0x01, 50), /* Target temperature */<br>+ HWM_INITVAL(0x02, 0x40), /* Enable Smart Fan IV mode */<br>+ HWM_INITVAL(0x03, 0x01), /* Step-up time */<br>+ HWM_INITVAL(0x04, 0x01), /* Step-down time */<br>+ HWM_INITVAL(0x05, 0x10), /* Stop PWM value */<br>+ HWM_INITVAL(0x06, 0x20), /* Start PWM value */<br>+ HWM_INITVAL(0x21, 45), /* Smart Fan IV Temp1 */<br>+ HWM_INITVAL(0x22, 46), /* Smart Fan IV Temp2 */<br>+ HWM_INITVAL(0x23, 47), /* Smart Fan IV Temp3 */<br>+ HWM_INITVAL(0x24, PASSIVE_TEMPERATURE), /* Smart Fan IV Temp4 */<br>+ HWM_INITVAL(0x27, 0x01), /* Smart Fan IV PWM1 */<br>+ HWM_INITVAL(0x28, 0x02), /* Smart Fan IV PWM2 */<br>+ HWM_INITVAL(0x29, 0x03), /* Smart Fan IV PWM3 */<br>+ HWM_INITVAL(0x2a, 0xff), /* Smart Fan IV PWM4 */<br>+ /* Smart Fan IV Critical temp */<br>+ HWM_INITVAL(0x35, CRITICAL_TEMPERATURE),<br>+ HWM_INITVAL(0x38, 3), /* Smart Fan IV Critical temp tolerance */<br>+ HWM_INITVAL(0x39, 0x81), /* Enable SYSTIN weight value */<br>+ HWM_INITVAL(0x3a, 1), /* SYSTIN temperature step */<br>+ HWM_INITVAL(0x3b, 2), /* SYSTIN step tolerance */<br>+ HWM_INITVAL(0x3c, 1), /* SYSTIN weight step */<br>+ HWM_INITVAL(0x3d, 40), /* SYSTIN temperature base */<br>+ HWM_INITVAL(0x3e, 0x00), /* SYSTIN fan duty base */<br>+<br>+ HWM_BANK(0),<br>+};<br>+<br>+static void hwm_init(void)<br>+{<br>+ /* Set up fan control */<br>+ for (int i = 0; i < ARRAY_SIZE(hwm_initvals); i++)<br>+ HWM_WRITE_INITVAL(hwm_initvals[i]);<br>+}<br>+<br>+static const u16 superio_initvals[] = {<br>+ /* Global config registers */<br>+ SUPERIO_INITVAL(0x1a, 0x02),<br>+ SUPERIO_INITVAL(0x1b, 0x6a),<br>+ SUPERIO_INITVAL(0x27, 0x80),<br>+#if IS_ENABLED(CONFIG_ENABLE_UART_ON_TESTPADS)<br>+ SUPERIO_INITVAL(0x2a, 0x00),<br>+#else<br>+ SUPERIO_INITVAL(0x2a, 0x80),<br>+#endif<br>+ SUPERIO_INITVAL(0x2c, 0x00),<br>+<br>+ SUPERIO_BANK(2), /* UART A */<br>+ SUPERIO_INITVAL(0x30, 0x01),<br>+ SUPERIO_INITVAL(0x60, 0x03),<br>+ SUPERIO_INITVAL(0x61, 0xf8),<br>+ SUPERIO_INITVAL(0x70, 0x04),<br>+<br>+ SUPERIO_BANK(7), /* GPIO config */<br>+ SUPERIO_INITVAL(0x30, 0x01),<br>+ SUPERIO_INITVAL(0xe0, 0xcf),<br>+ SUPERIO_INITVAL(0xe1, 0x0f),<br>+ SUPERIO_INITVAL(0xe4, 0xed),<br>+ SUPERIO_INITVAL(0xe5, 0x4d),<br>+ SUPERIO_INITVAL(0xec, 0x30),<br>+ SUPERIO_INITVAL(0xee, 0xff),<br>+<br>+ SUPERIO_BANK(8),<br>+ SUPERIO_INITVAL(0x30, 0x06),<br>+ SUPERIO_INITVAL(0x60, GPIO_PORT >> 8),<br>+ SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff),<br>+<br>+ SUPERIO_BANK(9),<br>+ SUPERIO_INITVAL(0x30, 0x8c),<br>+ SUPERIO_INITVAL(0xe1, 0x90),<br>+<br>+ SUPERIO_BANK(0xa),<br>+ SUPERIO_INITVAL(0xe4, 0x20),<br>+ SUPERIO_INITVAL(0xe6, 0x4c),<br>+<br>+ SUPERIO_BANK(0xb), /* HWM & LED */<br>+ SUPERIO_INITVAL(0x30, 0x01),<br>+ SUPERIO_INITVAL(0x60, HWM_PORT >> 8),<br>+ SUPERIO_INITVAL(0x61, HWM_PORT & 0xff),<br>+ SUPERIO_INITVAL(0xf7, 0x67),<br>+ SUPERIO_INITVAL(0xf8, 0x60),<br>+<br>+ SUPERIO_BANK(0x16),<br>+ SUPERIO_INITVAL(0x30, 0x00),<br>+};<br>+<br>+static void superio_init(void)<br>+{<br>+ SUPERIO_UNLOCK;<br>+ for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++)<br>+ SUPERIO_WRITE_INITVAL(superio_initvals[i]);<br>+ SUPERIO_LOCK;<br>+}<br>+<br>+void mainboard_config_superio(void)<br>+{<br>+ superio_init();<br>+ hwm_init();<br>+}<br>+<br>+void mainboard_get_spd(spd_raw_data *spd, bool id_only)<br>+{<br>+ read_spd(&spd[0], 0x50, id_only);<br>+ read_spd(&spd[2], 0x51, id_only);<br>+}<br>+<br>+const struct southbridge_usb_port mainboard_usb_ports[] = {<br>+#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }<br>+#include "usb.h"<br>+};<br>diff --git a/src/mainboard/intel/dcp847ske/gma-mainboard.ads b/src/mainboard/intel/dcp847ske/gma-mainboard.ads<br>new file mode 100644<br>index 0000000..493051e<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/gma-mainboard.ads<br>@@ -0,0 +1,28 @@<br>+-- This file is part of the coreboot project.<br>+--<br>+-- Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+--<br>+-- This program is free software; you can redistribute it and/or<br>+-- modify it under the terms of the GNU General Public License as<br>+-- published by the Free Software Foundation; version 2 of<br>+-- the License.<br>+--<br>+-- This program is distributed in the hope that it will be useful,<br>+-- but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+-- GNU General Public License for more details.<br>+<br>+with HW.GFX.GMA;<br>+with HW.GFX.GMA.Display_Probing;<br>+<br>+use HW.GFX.GMA;<br>+use HW.GFX.GMA.Display_Probing;<br>+<br>+private package GMA.Mainboard is<br>+<br>+ ports : constant Port_List :=<br>+ (HDMI1,<br>+ HDMI3,<br>+ others => Disabled);<br>+<br>+end GMA.Mainboard;<br>diff --git a/src/mainboard/intel/dcp847ske/gnvs.c b/src/mainboard/intel/dcp847ske/gnvs.c<br>new file mode 100644<br>index 0000000..e92c421<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/gnvs.c<br>@@ -0,0 +1,37 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/bd82x6x/nvs.h><br>+#include "thermal.h"<br>+<br>+/* FIXME: check this function. */<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+ /* Disable USB ports in S3 by default */<br>+ gnvs->s3u0 = 0;<br>+ gnvs->s3u1 = 0;<br>+<br>+ /* Disable USB ports in S5 by default */<br>+ gnvs->s5u0 = 0;<br>+ gnvs->s5u1 = 0;<br>+<br>+ // No LID: open by default.<br>+ gnvs->lids = 1;<br>+<br>+ gnvs->tcrt = CRITICAL_TEMPERATURE;<br>+ gnvs->tpsv = PASSIVE_TEMPERATURE;<br>+}<br>diff --git a/src/mainboard/intel/dcp847ske/gpio.c b/src/mainboard/intel/dcp847ske/gpio.c<br>new file mode 100644<br>index 0000000..50da50e<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/gpio.c<br>@@ -0,0 +1,209 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/common/gpio.h><br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_NATIVE,<br>+ .gpio1 = GPIO_MODE_GPIO,<br>+ .gpio2 = GPIO_MODE_GPIO,<br>+ .gpio3 = GPIO_MODE_GPIO,<br>+ .gpio4 = GPIO_MODE_GPIO,<br>+ .gpio5 = GPIO_MODE_NATIVE,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio9 = GPIO_MODE_NATIVE,<br>+ .gpio10 = GPIO_MODE_NATIVE,<br>+ .gpio11 = GPIO_MODE_NATIVE,<br>+ .gpio12 = GPIO_MODE_NATIVE,<br>+ .gpio13 = GPIO_MODE_NATIVE,<br>+ .gpio14 = GPIO_MODE_NATIVE,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_NATIVE,<br>+ .gpio17 = GPIO_MODE_GPIO,<br>+ .gpio18 = GPIO_MODE_NATIVE,<br>+ .gpio19 = GPIO_MODE_NATIVE,<br>+ .gpio20 = GPIO_MODE_GPIO,<br>+ .gpio21 = GPIO_MODE_NATIVE,<br>+ .gpio22 = GPIO_MODE_GPIO,<br>+ .gpio23 = GPIO_MODE_NATIVE,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio25 = GPIO_MODE_NATIVE,<br>+ .gpio26 = GPIO_MODE_NATIVE,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+ .gpio29 = GPIO_MODE_GPIO,<br>+ .gpio30 = GPIO_MODE_NATIVE,<br>+ .gpio31 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio1 = GPIO_DIR_INPUT,<br>+ .gpio2 = GPIO_DIR_INPUT,<br>+ .gpio3 = GPIO_DIR_INPUT,<br>+ .gpio4 = GPIO_DIR_INPUT,<br>+ .gpio6 = GPIO_DIR_INPUT,<br>+ .gpio7 = GPIO_DIR_INPUT,<br>+ .gpio8 = GPIO_DIR_OUTPUT,<br>+ .gpio15 = GPIO_DIR_OUTPUT,<br>+ .gpio17 = GPIO_DIR_INPUT,<br>+ .gpio20 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_INPUT, /* BIOS jumper: 1 = normal, 0 = setup */<br>+ .gpio24 = GPIO_DIR_OUTPUT,<br>+ .gpio27 = GPIO_DIR_OUTPUT,<br>+ .gpio28 = GPIO_DIR_OUTPUT,<br>+ .gpio29 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+/*<br>+ * GPIO8: HIGH crashes kernel, maybe selects 1.35V for RAM<br>+ * GPIO27: Set to HIGH on S3/S4/S5 by original fw dsdt.<br>+ * GPIO29: Actually NATIVE? Can't clear, stays 1.<br>+ * SLP_LAN# is affected by soft-strap according to docs.<br>+ * Others: No visible effect when toggling.<br>+ */<br>+static const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio8 = GPIO_LEVEL_LOW,<br>+ .gpio15 = GPIO_LEVEL_HIGH,<br>+ .gpio24 = GPIO_LEVEL_HIGH,<br>+ .gpio27 = GPIO_LEVEL_LOW,<br>+ .gpio28 = GPIO_LEVEL_HIGH,<br>+ .gpio29 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_reset = {<br>+ .gpio30 = GPIO_RESET_RSMRST,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio32 = GPIO_MODE_NATIVE,<br>+ .gpio33 = GPIO_MODE_NATIVE,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_GPIO,<br>+ .gpio37 = GPIO_MODE_GPIO,<br>+ .gpio38 = GPIO_MODE_GPIO,<br>+ .gpio39 = GPIO_MODE_GPIO,<br>+ .gpio40 = GPIO_MODE_NATIVE,<br>+ .gpio41 = GPIO_MODE_NATIVE,<br>+ .gpio42 = GPIO_MODE_NATIVE,<br>+ .gpio43 = GPIO_MODE_NATIVE,<br>+ .gpio44 = GPIO_MODE_NATIVE,<br>+ .gpio45 = GPIO_MODE_NATIVE,<br>+ .gpio46 = GPIO_MODE_NATIVE,<br>+ .gpio47 = GPIO_MODE_NATIVE,<br>+ .gpio48 = GPIO_MODE_GPIO,<br>+ .gpio49 = GPIO_MODE_GPIO,<br>+ .gpio50 = GPIO_MODE_NATIVE,<br>+ .gpio51 = GPIO_MODE_NATIVE,<br>+ .gpio52 = GPIO_MODE_NATIVE,<br>+ .gpio53 = GPIO_MODE_GPIO,<br>+ .gpio54 = GPIO_MODE_NATIVE,<br>+ .gpio55 = GPIO_MODE_GPIO,<br>+ .gpio56 = GPIO_MODE_NATIVE,<br>+ .gpio57 = GPIO_MODE_GPIO,<br>+ .gpio58 = GPIO_MODE_NATIVE,<br>+ .gpio59 = GPIO_MODE_NATIVE,<br>+ .gpio60 = GPIO_MODE_NATIVE,<br>+ .gpio61 = GPIO_MODE_NATIVE,<br>+ .gpio62 = GPIO_MODE_NATIVE,<br>+ .gpio63 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio34 = GPIO_DIR_OUTPUT,<br>+ .gpio35 = GPIO_DIR_INPUT, /* mSATA presence detect */<br>+ .gpio36 = GPIO_DIR_INPUT,<br>+ .gpio37 = GPIO_DIR_OUTPUT,<br>+ .gpio38 = GPIO_DIR_INPUT,<br>+ .gpio39 = GPIO_DIR_INPUT,<br>+ .gpio48 = GPIO_DIR_INPUT,<br>+ .gpio49 = GPIO_DIR_INPUT,<br>+ .gpio53 = GPIO_DIR_OUTPUT,<br>+ .gpio55 = GPIO_DIR_OUTPUT,<br>+ .gpio57 = GPIO_DIR_INPUT,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio34 = GPIO_LEVEL_LOW,<br>+ .gpio37 = GPIO_LEVEL_LOW,<br>+ .gpio53 = GPIO_LEVEL_HIGH,<br>+ .gpio55 = GPIO_LEVEL_LOW,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_reset = {<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_mode = {<br>+ .gpio64 = GPIO_MODE_NATIVE,<br>+ .gpio65 = GPIO_MODE_NATIVE,<br>+ .gpio66 = GPIO_MODE_GPIO,<br>+ .gpio67 = GPIO_MODE_GPIO,<br>+ .gpio68 = GPIO_MODE_GPIO,<br>+ .gpio69 = GPIO_MODE_GPIO,<br>+ .gpio70 = GPIO_MODE_NATIVE,<br>+ .gpio71 = GPIO_MODE_NATIVE,<br>+ .gpio72 = GPIO_MODE_NATIVE,<br>+ .gpio73 = GPIO_MODE_NATIVE,<br>+ .gpio74 = GPIO_MODE_NATIVE,<br>+ .gpio75 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_direction = {<br>+ .gpio66 = GPIO_DIR_OUTPUT,<br>+ .gpio67 = GPIO_DIR_INPUT,<br>+ .gpio68 = GPIO_DIR_OUTPUT,<br>+ .gpio69 = GPIO_DIR_INPUT,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_level = {<br>+ .gpio66 = GPIO_LEVEL_LOW,<br>+ .gpio68 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_reset = {<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ .reset = &pch_gpio_set1_reset,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ .reset = &pch_gpio_set2_reset,<br>+ },<br>+ .set3 = {<br>+ .mode = &pch_gpio_set3_mode,<br>+ .direction = &pch_gpio_set3_direction,<br>+ .level = &pch_gpio_set3_level,<br>+ .reset = &pch_gpio_set3_reset,<br>+ },<br>+};<br>diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c<br>new file mode 100644<br>index 0000000..b000347<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/hda_verb.c<br>@@ -0,0 +1,40 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+ 0x80862806, /* Codec Vendor / Device ID: Intel */<br>+ 0x80860101, /* Subsystem ID */<br>+<br>+ 0x00000004, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x3, 0x80860101),<br>+<br>+ /* NID 0x05. */<br>+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),<br>+<br>+ /* NID 0x06. */<br>+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),<br>+<br>+ /* NID 0x07. */<br>+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),<br>+};<br>+<br>+const u32 pc_beep_verbs[0] = {};<br>+<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c<br>new file mode 100644<br>index 0000000..96e6e54<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/mainboard.c<br>@@ -0,0 +1,40 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci_def.h><br>+#include <drivers/intel/gma/int15.h><br>+#include <southbridge/intel/bd82x6x/pch.h><br>+#include <southbridge/intel/common/gpio.h><br>+#include <smbios.h><br>+<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ printk(BIOS_DEBUG, "BIOS_CFG jumper: %s\n",<br>+ get_gpio(22) ? "normal (1-2)" : "setup (2-3)");<br>+ printk(BIOS_DEBUG, "mSATA: %s\n",<br>+ get_gpio(35) ? "present" : "absent");<br>+<br>+ install_intel_vga_int15_handler(<br>+ GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,<br>+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c<br>new file mode 100644<br>index 0000000..57d71c6<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/romstage.c<br>@@ -0,0 +1,63 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <northbridge/intel/sandybridge/sandybridge.h><br>+#include <northbridge/intel/sandybridge/raminit.h><br>+<br>+#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)<br>+void mainboard_fill_pei_data(struct pei_data *pei_data)<br>+{<br>+ struct pei_data pei_data_template = {<br>+ .pei_version = PEI_VERSION,<br>+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,<br>+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,<br>+ .epbar = DEFAULT_EPBAR,<br>+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,<br>+ .smbusbar = SMBUS_IO_BASE,<br>+ .wdbbar = 0x4000000,<br>+ .wdbsize = 0x1000,<br>+ .hpet_address = CONFIG_HPET_ADDRESS,<br>+ .rcba = (uintptr_t)DEFAULT_RCBABASE,<br>+ .pmbase = DEFAULT_PMBASE,<br>+ .gpiobase = DEFAULT_GPIOBASE,<br>+ .thermalbase = 0xfed08000,<br>+ .system_type = 0, // 0 Mobile, 1 Desktop/Server<br>+ .tseg_size = CONFIG_SMM_TSEG_SIZE,<br>+ .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },<br>+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },<br>+ .ec_present = 0,<br>+ .gbe_enable = 1,<br>+ // 0 = leave channel enabled<br>+ // 1 = disable dimm 0 on channel<br>+ // 2 = disable dimm 1 on channel<br>+ // 3 = disable dimm 0+1 on channel<br>+ .dimm_channel0_disabled = 2,<br>+ .dimm_channel1_disabled = 2,<br>+ .max_ddr3_freq = 1333,<br>+ .usb_port_config = {<br>+#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }<br>+#include "usb.h"<br>+ },<br>+ };<br>+ *pei_data = pei_data_template;<br>+}<br>+<br>+int mainboard_should_reset_usb(int s3resume)<br>+{<br>+ return !s3resume;<br>+}<br>+#endif<br>diff --git a/src/mainboard/intel/dcp847ske/smihandler.c b/src/mainboard/intel/dcp847ske/smihandler.c<br>new file mode 100644<br>index 0000000..8bd5c1c<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/smihandler.c<br>@@ -0,0 +1,34 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <cpu/x86/smm.h><br>+#include <device/pnp.h><br>+#include <ec/acpi/ec.h><br>+#include <superio/nuvoton/nct6776/nct6776.h><br>+#include <superio/nuvoton/common/nuvoton.h><br>+<br>+#include "superio.h"<br>+<br>+void mainboard_smi_sleep(u8 slp_typ)<br>+{<br>+ if (slp_typ != 0) {<br>+ /* Enable GRN_LED [Power LED] fading */<br>+ SUPERIO_UNLOCK;<br>+ SUPERIO_WRITE(0xf7, 0x68);<br>+ SUPERIO_LOCK;<br>+ }<br>+}<br>diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h<br>new file mode 100644<br>index 0000000..841353d<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/superio.h<br>@@ -0,0 +1,52 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef DCP847SKE_SUPERIO_H<br>+#define DCP847SKE_SUPERIO_H<br>+<br>+#define NUVOTON_PORT 0x4e<br>+#define HWM_PORT 0x0a30<br>+#define GPIO_PORT 0x0a80<br>+<br>+#define SUPERIO_BANK(x) (0x0700 | x)<br>+#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data))<br>+#define HWM_BANK(x) (0x4e00 | x)<br>+#define HWM_INITVAL SUPERIO_INITVAL<br>+<br>+#define SUPERIO_UNLOCK do { \<br>+ outb(0x87, NUVOTON_PORT); \<br>+ outb(0x87, NUVOTON_PORT); \<br>+} while (0)<br>+<br>+#define SUPERIO_LOCK do { \<br>+ outb(0xaa, NUVOTON_PORT); \<br>+} while (0)<br>+<br>+#define SUPERIO_WRITE(reg, data) do { \<br>+ outb((reg), NUVOTON_PORT); \<br>+ outb((data), NUVOTON_PORT + 1); \<br>+} while (0)<br>+<br>+#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff)<br>+<br>+#define HWM_WRITE(reg, data) do { \<br>+ outb((reg), HWM_PORT + 5); \<br>+ outb((data), HWM_PORT + 6); \<br>+} while (0)<br>+<br>+#define HWM_WRITE_INITVAL(val) HWM_WRITE((val) >> 8, (val) & 0xff)<br>+<br>+#endif /* DCP847SKE_SUPERIO_H */<br>diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h<br>new file mode 100644<br>index 0000000..e60daaa<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/thermal.h<br>@@ -0,0 +1,29 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef DCP847SKE_THERMAL_H<br>+#define DPC847SKE_THERMAL_H<br>+<br>+/* TODO: These should be generated at runtime from<br>+ * MSR_IA32_TEMPERATURE_TARGET (0x1a2) */<br>+<br>+/* Temperature which OS will shutdown at */<br>+#define CRITICAL_TEMPERATURE 100<br>+<br>+/* Temperature which OS will throttle CPU */<br>+#define PASSIVE_TEMPERATURE 86<br>+<br>+#endif<br>diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h<br>new file mode 100644<br>index 0000000..c6a5295<br>--- /dev/null<br>+++ b/src/mainboard/intel/dcp847ske/usb.h<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef DCP847SKE_USB_H<br>+#define DPC847SKE_USB_H<br>+<br>+USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */<br>+USB_CONFIG(1, 1, 0), /* back, towards power plug */<br>+USB_CONFIG(1, 1, 1), /* half-width miniPCIe */<br>+USB_CONFIG(1, 1, 1), /* full-width miniPCIe */<br>+USB_CONFIG(1, 1, 2), /* front-panel header */<br>+USB_CONFIG(1, 1, 2), /* front-panel header */<br>+USB_CONFIG(1, 1, 3), /* front connector */<br>+USB_CONFIG(0, 1, 3), /* not available */<br>+USB_CONFIG(0, 1, 4), /* not available */<br>+USB_CONFIG(0, 1, 4), /* not available */<br>+USB_CONFIG(0, 1, 5), /* not available */<br>+USB_CONFIG(0, 1, 5), /* not available */<br>+USB_CONFIG(0, 1, 6), /* not available */<br>+USB_CONFIG(0, 1, 6), /* not available */<br>+<br>+#endif<br>diff --git a/src/southbridge/intel/bd82x6x/acpi/gbe.asl b/src/southbridge/intel/bd82x6x/acpi/gbe.asl<br>new file mode 100644<br>index 0000000..e0a2460<br>--- /dev/null<br>+++ b/src/southbridge/intel/bd82x6x/acpi/gbe.asl<br>@@ -0,0 +1,60 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2017 coresystems GmbH<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Intel PCH Gigabit Ethernet 0:19.0 */<br>+<br>+Device (GLAN)<br>+{<br>+ Name (_ADR, 0x00190000)<br>+<br>+ // Power Resources for Wake<br>+ Name (_PRW, Package(){<br>+ 13, // Bit 13 of GPE<br>+ 4 // Can wake from S4 state.<br>+ })<br>+<br>+ /*<br>+ * Device Specific Method<br>+ * Arg0 - UUID<br>+ * Arg1 - Revision<br>+ * Arg2 - Function Index<br>+ * Arg3 - Function Arg<br>+ */<br>+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method<br>+ {<br>+ // Device label GUID, used by systemd for naming.<br>+ If (Arg0 == ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))<br>+ {<br>+ Switch (ToInteger(Arg2)) {<br>+ // Function 0 (Report supported functions)<br>+ Case (0) {<br>+ // Supports functions 7 & 0<br>+ Return (Buffer() { 0x81 })<br>+ }<br>+ // Function 7 (DEVICE_LABEL_DSM)<br>+ Case (7) {<br>+ Return (Package(){<br>+ 1, // Instance number<br>+ "LAN", // Optional name<br>+ })<br>+ }<br>+ }<br>+ }<br>+<br>+ // No functions supported for the given GUID<br>+ Return (Buffer() { 0 })<br>+ }<br>+}<br>diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl<br>index cfa27d2..7d8d5df 100644<br>--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl<br>+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl<br>@@ -234,6 +234,9 @@<br> }<br> }<br> <br>+// Gigabit Ethernet 0:19.0<br>+#include "gbe.asl"<br>+<br> // High Definition Audio (Azalia) 0:1b.0<br> #include "audio.asl"<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22683">change 22683</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22683"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 </div>
<div style="display:none"> Gerrit-Change-Number: 22683 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tobias Diedrich <ranma+coreboot@tdiedrich.de> </div>