<p>Srinidhi N Kaushik would like Hannah Williams to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22639">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">acpi/cnvi.asl: Add _PRW for CNVi<br><br>Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3<br>Signed-off-by: Hannah Williams <hannah.williams@intel.com><br>---<br>A src/soc/intel/apollolake/acpi/cnvi.asl<br>M src/soc/intel/apollolake/acpi/southbridge.asl<br>M src/soc/intel/apollolake/include/soc/gpe.h<br>3 files changed, 37 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22639/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/acpi/cnvi.asl b/src/soc/intel/apollolake/acpi/cnvi.asl<br>new file mode 100644<br>index 0000000..5d3616c<br>--- /dev/null<br>+++ b/src/soc/intel/apollolake/acpi/cnvi.asl<br>@@ -0,0 +1,30 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* CNVi Controller 0:C.0 */<br>+Device (CNVI) {<br>+    Name(_ADR, 0x000C0000)<br>+<br>+   Name (_S3D, 3)  /* D3 supported in S3 */<br>+     Name (_S0W, 3)  /* D3 can wake device in S0 */<br>+       Name (_S3W, 3)  /* D3 can wake system from S3 */<br>+<br>+  Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 })<br>+<br>+  Method (_STA, 0)<br>+     {<br>+            Return (0xF)<br>+ }<br>+}<br>diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl<br>index 97a25a2..5b8f9b7 100644<br>--- a/src/soc/intel/apollolake/acpi/southbridge.asl<br>+++ b/src/soc/intel/apollolake/acpi/southbridge.asl<br>@@ -56,4 +56,10 @@<br> /* SGX */<br> #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)<br> #include <soc/intel/common/acpi/sgx.asl><br>+<br>+/* CNVi */<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#include "cnvi.asl"<br>+#endif<br>+<br> #endif<br>diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h<br>index 7dfb6f5..eb6e31f 100644<br>--- a/src/soc/intel/apollolake/include/soc/gpe.h<br>+++ b/src/soc/intel/apollolake/include/soc/gpe.h<br>@@ -33,6 +33,7 @@<br> #define GPE0A_GPIO_TIER1_SCI_STS      15<br> #define GPE0A_SMB_WAK_STS          16<br> #define GPE0A_SATA_PME_STS         17<br>+#define GPE0A_CNVI_PME_STS         18<br> <br> /* Group DW0 is reserved in Apollolake */<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22639">change 22639</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22639"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3 </div>
<div style="display:none"> Gerrit-Change-Number: 22639 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>