<p>Piotr Król has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22629">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">pcengines/apu2: add support for apu4 variant<br><br>apu4 is new version of PC Engines platform, which contain 4 Ethernet<br>port and 4GB of RAM. In functional way it is very similar to apu3.<br><br>Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7<br>Signed-off-by: Piotr Król <piotr.krol@3mdeb.com><br>---<br>M src/mainboard/pcengines/apu2/Kconfig<br>M src/mainboard/pcengines/apu2/Kconfig.name<br>M src/mainboard/pcengines/apu2/board_info.txt<br>M src/mainboard/pcengines/apu2/romstage.c<br>A src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb<br>5 files changed, 109 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/22629/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig<br>index 432963e..f9a87dd 100644<br>--- a/src/mainboard/pcengines/apu2/Kconfig<br>+++ b/src/mainboard/pcengines/apu2/Kconfig<br>@@ -14,7 +14,8 @@<br> # GNU General Public License for more details.<br> #<br> <br>-if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5<br>+if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \<br>+ BOARD_PCENGINES_APU5<br> <br> config BOARD_SPECIFIC_OPTIONS # dummy<br> def_bool y<br>@@ -41,6 +42,7 @@<br> string<br> default "apu2" if BOARD_PCENGINES_APU2<br> default "apu3" if BOARD_PCENGINES_APU3<br>+ default "apu4" if BOARD_PCENGINES_APU4<br> default "apu5" if BOARD_PCENGINES_APU5<br> <br> config DEVICETREE<br>@@ -51,6 +53,7 @@<br> string<br> default "apu2" if BOARD_PCENGINES_APU2<br> default "apu3" if BOARD_PCENGINES_APU3<br>+ default "apu4" if BOARD_PCENGINES_APU4<br> default "apu5" if BOARD_PCENGINES_APU5<br> <br> config MAX_CPUS<br>@@ -76,7 +79,7 @@<br> choice<br> prompt "J19 pins 1-10"<br> default APU2_PINMUX_OFF_C if BOARD_PCENGINES_APU2 || \<br>- BOARD_PCENGINES_APU3<br>+ BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4<br> default APU2_PINMUX_UART_C if BOARD_PCENGINES_APU5<br> <br> config APU2_PINMUX_OFF_C<br>@@ -84,7 +87,8 @@<br> <br> config APU2_PINMUX_GPIO0<br> bool "GPIO"<br>- depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3<br>+ depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \<br>+ BOARD_PCENGINES_APU4<br> <br> config APU2_PINMUX_UART_C<br> bool "UART 0x3e8"<br>@@ -94,7 +98,7 @@<br> choice<br> prompt "J19 pins 11-20"<br> default APU2_PINMUX_OFF_D if BOARD_PCENGINES_APU2 || \<br>- BOARD_PCENGINES_APU3<br>+ BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4<br> default APU2_PINMUX_UART_D if BOARD_PCENGINES_APU5<br> <br> config APU2_PINMUX_OFF_D<br>@@ -102,7 +106,8 @@<br> <br> config APU2_PINMUX_GPIO1<br> bool "GPIO"<br>- depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3<br>+ depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \<br>+ BOARD_PCENGINES_APU4<br> <br> config APU2_PINMUX_UART_D<br> bool "UART 0x2e8"<br>diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name<br>index 68e6d6e..45ec16f 100644<br>--- a/src/mainboard/pcengines/apu2/Kconfig.name<br>+++ b/src/mainboard/pcengines/apu2/Kconfig.name<br>@@ -4,5 +4,8 @@<br> config BOARD_PCENGINES_APU3<br> bool "APU3"<br> <br>+config BOARD_PCENGINES_APU4<br>+ bool "APU4"<br>+<br> config BOARD_PCENGINES_APU5<br> bool "APU5"<br>diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt<br>index f7d5172..ec2cc9d 100644<br>--- a/src/mainboard/pcengines/apu2/board_info.txt<br>+++ b/src/mainboard/pcengines/apu2/board_info.txt<br>@@ -1,4 +1,4 @@<br>-Board name: apu2 apu3 apu5<br>+Board name: apu2 apu3 apu4 apu5<br> Board URL: http://www.pcengines.ch/apu2c2.htm<br> Category: half<br> ROM package: SOIC-8<br>diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c<br>index 1433518..6339d94 100644<br>--- a/src/mainboard/pcengines/apu2/romstage.c<br>+++ b/src/mainboard/pcengines/apu2/romstage.c<br>@@ -117,7 +117,8 @@<br> // Configure output disabled, value low, pull up/down disabled<br> //<br> if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||<br>- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) {<br>+ IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||<br>+ IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {<br> configure_gpio(ACPI_MMIO_BASE,<br> IOMUX_GPIO_32, Function0, GPIO_32, setting);<br> }<br>@@ -129,7 +130,8 @@<br> // Configure output enabled, value low, pull up/down disabled<br> //<br> setting = 0x1 << GPIO_OUTPUT_ENABLE;<br>- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) {<br>+ if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||<br>+ IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {<br> configure_gpio(ACPI_MMIO_BASE,<br> IOMUX_GPIO_33, Function0, GPIO_33, setting);<br> }<br>diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb<br>new file mode 100644<br>index 0000000..9859255<br>--- /dev/null<br>+++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb<br>@@ -0,0 +1,91 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+chip northbridge/amd/pi/00730F01/root_complex<br>+ device cpu_cluster 0 on<br>+ chip cpu/amd/pi/00730F01<br>+ device lapic 0 on end<br>+ end<br>+ end<br>+<br>+ device domain 0 on<br>+ subsystemid 0x1022 0x1410 inherit<br>+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex<br>+<br>+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex<br>+ device pci 0.0 on end # Root Complex<br>+ device pci 0.2 off end # IOMMU<br>+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804<br>+ device pci 1.1 off end # Internal Multimedia<br>+ device pci 2.0 on end # PCIe Host Bridge<br>+ device pci 2.1 on end # LAN1<br>+ device pci 2.2 on end # LAN2<br>+ device pci 2.3 on end # LAN3<br>+ device pci 2.4 on end # LAN4<br>+ device pci 2.5 on end # mPCIe slot 1<br>+ device pci 8.0 on end # Platform Security Processor<br>+ end #chip northbridge/amd/pi/00730F01<br>+<br>+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus<br>+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2<br>+ device pci 11.0 on end # SATA<br>+ device pci 12.0 on end # USB EHCI0 usb[0:3] is connected<br>+ device pci 13.0 on end # USB EHCI1 usb[4:7]<br>+ device pci 14.0 on end # SM<br>+ device pci 14.3 on # LPC 0x439d<br>+ chip superio/nuvoton/nct5104d # SIO NCT5104D<br>+ register "irq_trigger_type" = "0"<br>+ device pnp 2e.0 off end<br>+ device pnp 2e.2 on<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.3 on<br>+ io 0x60 = 0x2f8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.10 on<br>+ # UART C is conditionally turned on<br>+ io 0x60 = 0x3e8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.11 on<br>+ # UART D is conditionally turned on<br>+ io 0x60 = 0x2e8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.8 off end<br>+ device pnp 2e.f off end<br>+ # GPIO0 and GPIO1 are conditionally turned on<br>+ device pnp 2e.007 on end<br>+ device pnp 2e.107 on end<br>+ device pnp 2e.607 off end<br>+ device pnp 2e.e off end<br>+ end # SIO NCT5104D<br>+ end # LPC 0x439d<br>+<br>+ device pci 14.7 on end # SD<br>+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI<br>+ end #chip southbridge/amd/pi/hudson<br>+<br>+ device pci 18.0 on end<br>+ device pci 18.1 on end<br>+ device pci 18.2 on end<br>+ device pci 18.3 on end<br>+ device pci 18.4 on end<br>+ device pci 18.5 on end<br>+<br>+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex<br>+ end #domain<br>+end #northbridge/amd/pi/00730F01/root_complex<br></pre><p>To view, visit <a href="https://review.coreboot.org/22629">change 22629</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7 </div>
<div style="display:none"> Gerrit-Change-Number: 22629 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Piotr Król <piotr.krol@3mdeb.com> </div>