<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22615">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Make use of Intel common Graphics block<br><br>TEST=Build and boot soraka/eve.<br><br>Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/Makefile.inc<br>A src/soc/intel/skylake/graphics.c<br>D src/soc/intel/skylake/igd.c<br>4 files changed, 116 insertions(+), 194 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/22615/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig<br>index e5cc4f7..8bf9b53 100644<br>--- a/src/soc/intel/skylake/Kconfig<br>+++ b/src/soc/intel/skylake/Kconfig<br>@@ -60,6 +60,7 @@<br> select SOC_INTEL_COMMON_BLOCK_GPIO<br> select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL<br> select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS<br>+ select SOC_INTEL_COMMON_BLOCK_GRAPHICS<br> select SOC_INTEL_COMMON_BLOCK_GSPI<br> select SOC_INTEL_COMMON_BLOCK_ITSS<br> select SOC_INTEL_COMMON_BLOCK_I2C<br>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc<br>index da45ec5..9f33114 100644<br>--- a/src/soc/intel/skylake/Makefile.inc<br>+++ b/src/soc/intel/skylake/Makefile.inc<br>@@ -52,7 +52,7 @@<br> ramstage-y += gpio.c<br> ramstage-y += gspi.c<br> ramstage-y += i2c.c<br>-ramstage-y += igd.c<br>+ramstage-y += graphics.c<br> ramstage-y += irq.c<br> ramstage-y += lockdown.c<br> ramstage-y += lpc.c<br>diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c<br>new file mode 100644<br>index 0000000..d4cb6e7<br>--- /dev/null<br>+++ b/src/soc/intel/skylake/graphics.c<br>@@ -0,0 +1,114 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <device/pci.h><br>+#include <drivers/intel/gma/i915_reg.h><br>+#include <intelblocks/graphics.h><br>+#include <soc/intel/common/opregion.h><br>+#include <soc/ramstage.h><br>+<br>+uintptr_t fsp_soc_get_igd_bar(void)<br>+{<br>+ return graphics_get_memory_base();<br>+}<br>+<br>+void graphics_soc_init(struct device *dev)<br>+{<br>+ u32 ddi_buf_ctl;<br>+<br>+ /*<br>+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.<br>+ * This will allow the kernel to use 4-lane eDP links properly<br>+ * if the VBIOS or GOP driver does not execute.<br>+ */<br>+ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);<br>+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {<br>+ ddi_buf_ctl |= DDI_A_4_LANES;<br>+ graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);<br>+ }<br>+<br>+ if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))<br>+ return;<br>+<br>+ /* IGD needs to be Bus Master */<br>+ u32 reg32 = pci_read_config32(dev, PCI_COMMAND);<br>+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;<br>+ pci_write_config32(dev, PCI_COMMAND, reg32);<br>+<br>+ /* Initialize PCI device, load/execute BIOS Option ROM */<br>+ pci_dev_init(dev);<br>+}<br>+<br>+/* Initialize IGD OpRegion, called from ACPI code */<br>+static int update_igd_opregion(igd_opregion_t *opregion)<br>+{<br>+ u16 reg16;<br>+<br>+ /* Initialize Mailbox 3 */<br>+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;<br>+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;<br>+ opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */<br>+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;<br>+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;<br>+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;<br>+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;<br>+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;<br>+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;<br>+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;<br>+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;<br>+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;<br>+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;<br>+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;<br>+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;<br>+<br>+ /* TODO This may need to happen in S3 resume */<br>+ pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion);<br>+ reg16 = pci_read_config16(SA_DEV_IGD, SWSCI);<br>+ reg16 &= ~GSSCIE;<br>+ reg16 |= SMISCISEL;<br>+ pci_write_config16(SA_DEV_IGD, SWSCI, reg16);<br>+<br>+ return 0;<br>+}<br>+<br>+uintptr_t graphics_soc_write_acpi_opregion(device_t device,<br>+ uintptr_t current, struct acpi_rsdp *rsdp)<br>+{<br>+ igd_opregion_t *opregion;<br>+<br>+ /* If GOP is not used, exit here */<br>+ if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))<br>+ return current;<br>+<br>+ /* If IGD is disabled, exit here */<br>+ if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)<br>+ return current;<br>+<br>+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");<br>+ opregion = (igd_opregion_t *)current;<br>+<br>+ if (init_igd_opregion(opregion) != CB_SUCCESS)<br>+ return current;<br>+<br>+ update_igd_opregion(opregion);<br>+ current += sizeof(igd_opregion_t);<br>+ current = acpi_align_current(current);<br>+<br>+ printk(BIOS_DEBUG, "current = %lx\n", current);<br>+ return current;<br>+}<br>diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c<br>deleted file mode 100644<br>index 545030f..0000000<br>--- a/src/soc/intel/skylake/igd.c<br>+++ /dev/null<br>@@ -1,193 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2014 Google Inc.<br>- * Copyright (C) 2015 Intel Corporation.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/acpi.h><br>-#include <arch/io.h><br>-#include <bootmode.h><br>-#include <chip.h><br>-#include <console/console.h><br>-#include <delay.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <drivers/intel/gma/i915_reg.h><br>-#include <soc/intel/common/opregion.h><br>-#include <soc/acpi.h><br>-#include <soc/cpu.h><br>-#include <soc/pm.h><br>-#include <soc/ramstage.h><br>-#include <soc/systemagent.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include <security/vboot/vbnv.h><br>-<br>-uintptr_t fsp_soc_get_igd_bar(void)<br>-{<br>- device_t dev = SA_DEV_IGD;<br>-<br>- /* Check if IGD PCI device is disabled */<br>- if (!dev->enabled)<br>- return 0;<br>-<br>- return find_resource(dev, PCI_BASE_ADDRESS_2)->base;<br>-}<br>-<br>-u32 map_oprom_vendev(u32 vendev)<br>-{<br>- return SA_IGD_OPROM_VENDEV;<br>-}<br>-<br>-static struct resource *gtt_res = NULL;<br>-<br>-static unsigned long gtt_read(unsigned long reg)<br>-{<br>- u32 val;<br>- val = read32((void *)(unsigned int)(gtt_res->base + reg));<br>- return val;<br>-}<br>-<br>-static void gtt_write(unsigned long reg, unsigned long data)<br>-{<br>- write32((void *)(unsigned int)(gtt_res->base + reg), data);<br>-}<br>-<br>-static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)<br>-{<br>- u32 val = gtt_read(reg);<br>- val &= andmask;<br>- val |= ormask;<br>- gtt_write(reg, val);<br>-}<br>-<br>-static void igd_init(struct device *dev)<br>-{<br>- u32 ddi_buf_ctl;<br>-<br>- gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- if (!gtt_res || !gtt_res->base)<br>- return;<br>-<br>- /*<br>- * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.<br>- * This will allow the kernel to use 4-lane eDP links properly<br>- * if the VBIOS or GOP driver does not execute.<br>- */<br>- ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A);<br>- if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {<br>- ddi_buf_ctl |= DDI_A_4_LANES;<br>- gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);<br>- }<br>-<br>- if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))<br>- return;<br>-<br>- /* IGD needs to be Bus Master */<br>- u32 reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>-<br>- /* Initialize PCI device, load/execute BIOS Option ROM */<br>- pci_dev_init(dev);<br>-}<br>-<br>-/* Initialize IGD OpRegion, called from ACPI code */<br>-static int update_igd_opregion(igd_opregion_t *opregion)<br>-{<br>- u16 reg16;<br>-<br>- /* Initialize Mailbox 3 */<br>- opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;<br>- opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;<br>- opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */<br>- opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;<br>- opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;<br>- opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;<br>- opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;<br>- opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;<br>- opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;<br>- opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;<br>- opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;<br>- opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;<br>- opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;<br>- opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;<br>- opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;<br>-<br>- /* TODO This may need to happen in S3 resume */<br>- pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion);<br>- reg16 = pci_read_config16(SA_DEV_IGD, SWSCI);<br>- reg16 &= ~GSSCIE;<br>- reg16 |= SMISCISEL;<br>- pci_write_config16(SA_DEV_IGD, SWSCI, reg16);<br>-<br>- return 0;<br>-}<br>-<br>-static unsigned long write_acpi_igd_opregion(device_t device,<br>- unsigned long current, struct acpi_rsdp *rsdp)<br>-{<br>- igd_opregion_t *opregion;<br>-<br>- /* If GOP is not used, exit here */<br>- if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))<br>- return current;<br>-<br>- /* If IGD is disabled, exit here */<br>- if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)<br>- return current;<br>-<br>- printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");<br>- opregion = (igd_opregion_t *)current;<br>-<br>- if (init_igd_opregion(opregion) != CB_SUCCESS)<br>- return current;<br>-<br>- update_igd_opregion(opregion);<br>- current += sizeof(igd_opregion_t);<br>- current = acpi_align_current(current);<br>-<br>- printk(BIOS_DEBUG, "current = %lx\n", current);<br>- return current;<br>-}<br>-<br>-static struct device_operations igd_ops = {<br>- .read_resources = &pci_dev_read_resources,<br>- .set_resources = &pci_dev_set_resources,<br>- .enable_resources = &pci_dev_enable_resources,<br>- .init = &igd_init,<br>- .ops_pci = &soc_pci_ops,<br>- .write_acpi_tables = write_acpi_igd_opregion,<br>-};<br>-<br>-static const unsigned short pci_device_ids[] = {<br>- PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM,<br>- PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM,<br>- PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM,<br>- PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,<br>- PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,<br>- PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,<br>- PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM,<br>- PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,<br>- PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM,<br>- PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR,<br>- PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM,<br>- 0,<br>-};<br>-<br>-static const struct pci_driver igd_driver __pci_driver = {<br>- .ops = &igd_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .devices = pci_device_ids,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22615">change 22615</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22615"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 </div>
<div style="display:none"> Gerrit-Change-Number: 22615 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>