<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22614">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Add Intel common Graphics controller support<br><br>SoC need to select specific macros to compile common<br>graphics code.<br><br>Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A src/soc/intel/common/block/graphics/Kconfig<br>A src/soc/intel/common/block/graphics/Makefile.inc<br>A src/soc/intel/common/block/graphics/graphics.c<br>A src/soc/intel/common/block/include/intelblocks/graphics.h<br>4 files changed, 184 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/22614/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig<br>new file mode 100644<br>index 0000000..4ab9200<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/graphics/Kconfig<br>@@ -0,0 +1,4 @@<br>+config SOC_INTEL_COMMON_BLOCK_GRAPHICS<br>+ bool<br>+ help<br>+ Intel Processor common Graphics support<br>diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc<br>new file mode 100644<br>index 0000000..44dfc7e<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/graphics/Makefile.inc<br>@@ -0,0 +1 @@<br>+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c<br>diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c<br>new file mode 100644<br>index 0000000..f35725c<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/graphics/graphics.c<br>@@ -0,0 +1,128 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <intelblocks/graphics.h><br>+#include <soc/pci_devs.h><br>+<br>+/* SoC Overrides */<br>+__attribute__((weak)) void graphics_soc_init(struct device *dev)<br>+{<br>+ /* no-op */<br>+}<br>+<br>+__attribute__((weak)) uintptr_t graphics_soc_write_acpi_opregion(<br>+ device_t device, uintptr_t current,<br>+ struct acpi_rsdp *rsdp)<br>+{<br>+ return 0;<br>+}<br>+<br>+uintptr_t graphics_get_memory_base(void)<br>+{<br>+ struct device *dev = SA_DEV_IGD;<br>+ struct resource *gm_res;<br>+<br>+ /*<br>+ * GFX PCI config space offset 0x18 know as Graphics<br>+ * Memory Range Address (GMADR)<br>+ */<br>+ gm_res = find_resource(dev, PCI_BASE_ADDRESS_2);<br>+ if (!gm_res || !gm_res->base)<br>+ return 0;<br>+<br>+ return gm_res->base;<br>+}<br>+<br>+static uintptr_t graphics_get_gtt_base(void)<br>+{<br>+ struct device *dev = SA_DEV_IGD;<br>+ struct resource *gtt_res;<br>+<br>+ /*<br>+ * GFX PCI config space offset 0x10 know as Graphics<br>+ * Translation Table Memory Mapped Range Address<br>+ * (GTTMMADR)<br>+ */<br>+ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>+ if (!gtt_res || !gtt_res->base)<br>+ return 0;<br>+<br>+ return gtt_res->base;<br>+}<br>+<br>+uintptr_t graphics_gtt_read(uintptr_t reg)<br>+{<br>+ uint32_t val;<br>+ val = read32((void *)(graphics_get_gtt_base() + reg));<br>+ return val;<br>+}<br>+<br>+void graphics_gtt_write(uintptr_t reg, uintptr_t data)<br>+{<br>+ write32((void *)(graphics_get_gtt_base() + reg), data);<br>+}<br>+<br>+void graphics_gtt_rmw(uint32_t reg, uint32_t andmask, uint32_t ormask)<br>+{<br>+ uint32_t val = graphics_gtt_read(reg);<br>+ val &= andmask;<br>+ val |= ormask;<br>+ graphics_gtt_write(reg, val);<br>+}<br>+<br>+static const struct device_operations graphics_ops = {<br>+ .read_resources = pci_dev_read_resources,<br>+ .set_resources = pci_dev_set_resources,<br>+ .enable_resources = pci_dev_enable_resources,<br>+ .init = graphics_soc_init,<br>+ .write_acpi_tables = graphics_soc_write_acpi_opregion,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+ PCI_DEVICE_ID_INTEL_APL_IGD_HD_505,<br>+ PCI_DEVICE_ID_INTEL_APL_IGD_HD_500,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,<br>+ PCI_DEVICE_ID_INTEL_GLK_IGD,<br>+ PCI_DEVICE_ID_INTEL_GLK_IGD_EU12,<br>+ PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM,<br>+ PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,<br>+ PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM,<br>+ PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR,<br>+ PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM,<br>+ PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM,<br>+ PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM,<br>+ PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM,<br>+ PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,<br>+ PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,<br>+ PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,<br>+ 0,<br>+};<br>+<br>+static const struct pci_driver graphics_driver __pci_driver = {<br>+ .ops = &graphics_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br>diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h<br>new file mode 100644<br>index 0000000..69a1f36<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/include/intelblocks/graphics.h<br>@@ -0,0 +1,51 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_H<br>+#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H<br>+<br>+/*<br>+ * SoC overrides<br>+ *<br>+ * All new SoC must implement below functionality.<br>+ */<br>+<br>+/*<br>+ * Perform Graphics Initialization in ramstage<br>+ * Input:<br>+ * struct device *dev: device structure<br>+ */<br>+void graphics_soc_init(struct device *dev);<br>+<br>+/*<br>+ * Write ASL entry for Graphics opregion<br>+ * Input:<br>+ * device_t device: device structure<br>+ * current: start address of graphics opregion<br>+ * rsdp: pointer to RSDT (and XSDT) structure<br>+ *<br>+ * Output:<br>+ * 0 = Error, >0 = End address of graphics opregion<br>+ */<br>+uintptr_t graphics_soc_write_acpi_opregion(device_t device,<br>+ uintptr_t current, struct acpi_rsdp *rsdp);<br>+<br>+/* Graphics MMIO register read/write APIs */<br>+uintptr_t graphics_gtt_read(uintptr_t reg);<br>+void graphics_gtt_write(uintptr_t reg, uintptr_t data);<br>+void graphics_gtt_rmw(uint32_t reg, uint32_t andmask, uint32_t ormask);<br>+uintptr_t graphics_get_memory_base(void);<br>+<br>+#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */<br></pre><p>To view, visit <a href="https://review.coreboot.org/22614">change 22614</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 </div>
<div style="display:none"> Gerrit-Change-Number: 22614 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>