<p>Divya Chellappa has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22587">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soraka: move WLAN_PE_RST gpio pad entry to early_gpio_table<br><br>RSMRST reset config doesn't preserve the gpio configuration<br>across deepSx, in such scenarios, gpio pad configuration<br>should be done in early pad configuration in bootblock.<br><br>BUG=none<br>BRANCH=none<br>TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.<br><br>Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6<br>Signed-off-by: Divya Chellap <divya.chellappa@intel.com><br>---<br>M src/mainboard/google/poppy/variants/soraka/gpio.c<br>1 file changed, 3 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22587/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>index 84a8294..ae1d07d 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/gpio.c<br>+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>@@ -78,8 +78,7 @@<br>    PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),<br>  /* B7  : SRCCLKREQ2# ==> NC */<br>     PAD_CFG_NC(GPP_B7),<br>-  /* B8  : SRCCLKREQ3# ==> WLAN_PE_RST */<br>-   PAD_CFG_GPO(GPP_B8, 0, RSMRST),<br>+<br>    /* B9  : SRCCLKREQ4# ==> NC */<br>     PAD_CFG_NC(GPP_B9),<br>   /* B10 : SRCCLKREQ5# ==> NC */<br>@@ -371,6 +370,8 @@<br> <br> /* Early pad configuration in bootblock */<br> static const struct pad_config early_gpio_table[] = {<br>+       /* B8  : SRCCLKREQ3# ==> WLAN_PE_RST */<br>+   PAD_CFG_GPO(GPP_B8, 0, RSMRST),<br> #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br>    /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>      PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>@@ -388,7 +389,6 @@<br>    /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>       PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br> #endif<br>-<br>     /* Ensure UART pins are in native mode for H1. */<br>     /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>       PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br></pre><p>To view, visit <a href="https://review.coreboot.org/22587">change 22587</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22587"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 </div>
<div style="display:none"> Gerrit-Change-Number: 22587 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Divya Chellappa <divya.chellappa@intel.com> </div>