<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22590">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Create new wide IO functions<br><br>Create new generic wide IO functions in southbridge.c. These new<br>functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c.<br><br>BUG=b:64033893<br><br>Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 134 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/22590/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 238feba..beb9af8 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -259,6 +259,12 @@<br> <br> #define FCH_MISC_REG40_OSCOUT1_EN BIT(2)<br> <br>+/* Return values for sb_find_wideio_range and sb_set_wideio_range. */<br>+#define WIDE_IO_RANGE_0 0x00<br>+#define WIDE_IO_RANGE_1 0x01<br>+#define WIDE_IO_RANGE_2 0x02<br>+#define WIDE_IO_RANGE_FAILED 0x80<br>+<br> static inline int sb_sata_enable(void)<br> {<br> /* True if IDE or AHCI. */<br>@@ -306,5 +312,8 @@<br> int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);<br> int s3_save_nvram_early(u32 dword, int size, int nvram_pos);<br> void bootblock_fch_early_init(void);<br>+uint16_t sb_wideio_size(uint8_t index);<br>+uint8_t sb_find_wideio_range(uint16_t start, uint16_t end);<br>+uint8_t sb_set_wideio_range(uint16_t start, uint16_t size);<br> <br> #endif /* __STONEYRIDGE_H__ */<br>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index dbf27bc..51e0e96 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -31,6 +31,131 @@<br> #include <delay.h><br> #include <soc/pci_devs.h><br> <br>+/*<br>+ * Structure to simplify code obtaining the total of used wide IO<br>+ * registers and the size assigned to each.<br>+ */<br>+static struct wide_IO_ioport_and_bits {<br>+ uint32_t enable[3];<br>+ uint16_t port[3];<br>+ uint8_t alt[3];<br>+} wio_io_en = {<br>+ {<br>+ LPC_WIDEIO0_ENABLE,<br>+ LPC_WIDEIO1_ENABLE,<br>+ LPC_WIDEIO2_ENABLE<br>+ },<br>+ {<br>+ LPC_WIDEIO_GENERIC_PORT,<br>+ LPC_WIDEIO1_GENERIC_PORT,<br>+ LPC_WIDEIO2_GENERIC_PORT<br>+ },<br>+ {<br>+ LPC_ALT_WIDEIO0_ENABLE,<br>+ LPC_ALT_WIDEIO1_ENABLE,<br>+ LPC_ALT_WIDEIO2_ENABLE<br>+ }<br>+};<br>+<br>+/**<br>+ * @brief Find the size of a particular wide IO<br>+ *<br>+ * @param index = index of desired wide IO<br>+ *<br>+ * @return size of desired wide IO<br>+ */<br>+uint16_t sb_wideio_size(uint8_t index)<br>+{<br>+ uint32_t enable_register;<br>+ uint16_t size = 0;<br>+ uint8_t alternate_register;<br>+<br>+ if (index < 3) {<br>+ enable_register = pci_read_config32(SOC_LPC_DEV,<br>+ LPC_IO_OR_MEM_DECODE_ENABLE);<br>+ alternate_register = pci_read_config8(SOC_LPC_DEV,<br>+ LPC_ALT_WIDEIO_RANGE_ENABLE);<br>+ if (enable_register & wio_io_en.enable[index])<br>+ size = (alternate_register & wio_io_en.alt[index]) ?<br>+ 16 : 512;<br>+ }<br>+ return size;<br>+}<br>+<br>+/**<br>+ * @brief Identify if any LPC wide IO is covering the IO range<br>+ *<br>+ * @param start = start of IO range<br>+ * @param end = end of IO range<br>+ *<br>+ * @return Index of wide IO covering the range or error<br>+ */<br>+uint8_t sb_find_wideio_range(uint16_t start, uint16_t end)<br>+{<br>+ uint32_t enable_register;<br>+ int i;<br>+ uint16_t reg_var[3], current_size;<br>+ uint16_t end_wideio;<br>+ uint8_t index = WIDE_IO_RANGE_FAILED;<br>+<br>+ enable_register = pci_read_config32(SOC_LPC_DEV,<br>+ LPC_IO_OR_MEM_DECODE_ENABLE);<br>+ for (i = 0; i < 3; i++)<br>+ reg_var[i] = pci_read_config16(SOC_LPC_DEV, wio_io_en.port[i]);<br>+<br>+ for (i = 0; i < 3; i++) {<br>+ current_size = sb_wideio_size(i);<br>+ if (current_size == 0)<br>+ continue;<br>+ end_wideio = reg_var[i] + current_size;<br>+ if ((start >= reg_var[i]) && (end <= end_wideio)) {<br>+ index = i;<br>+ break;<br>+ }<br>+ }<br>+ return index;<br>+}<br>+<br>+/**<br>+ * @brief Program a LPC wide IO to support an IO range<br>+ *<br>+ * @param start = start of range to be routed through wide IO<br>+ * @param size = size of range to be routed through wide IO<br>+ *<br>+ * @return Index of wide IO register used or error<br>+ */<br>+uint8_t sb_set_wideio_range(uint16_t start, uint16_t size)<br>+{<br>+ int i;<br>+ uint32_t enable_register;<br>+ uint8_t alternate_register;<br>+ uint8_t status = WIDE_IO_RANGE_FAILED;<br>+<br>+ enable_register = pci_read_config32(SOC_LPC_DEV,<br>+ LPC_IO_OR_MEM_DECODE_ENABLE);<br>+ alternate_register = pci_read_config8(SOC_LPC_DEV,<br>+ LPC_ALT_WIDEIO_RANGE_ENABLE);<br>+ for (i = 0; i < 3; i++) {<br>+ if ((enable_register & wio_io_en.enable[i]) == 0) {<br>+ status = i;<br>+ pci_write_config16(SOC_LPC_DEV, wio_io_en.port[i],<br>+ start);<br>+ enable_register |= wio_io_en.enable[i];<br>+ pci_write_config32(SOC_LPC_DEV,<br>+ LPC_IO_OR_MEM_DECODE_ENABLE,<br>+ enable_register);<br>+ if (size <= 16) {<br>+ alternate_register |= wio_io_en.alt[i];<br>+ pci_write_config8(SOC_LPC_DEV,<br>+ LPC_ALT_WIDEIO_RANGE_ENABLE,<br>+ alternate_register);<br>+ }<br>+ break;<br>+ }<br>+ }<br>+ return status;<br>+}<br>+<br> void configure_stoneyridge_uart(void)<br> {<br> u8 byte, byte2;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22590">change 22590</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22590"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 </div>
<div style="display:none"> Gerrit-Change-Number: 22590 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>