<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22564">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Make use of Intel common PMC common block<br><br>TEST=Build and boot reef<br><br>Change-Id: I968c88ef805fe58751f5359e27cbdf4d3fba3ae9<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/apollolake/pmc.c<br>1 file changed, 14 insertions(+), 82 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22564/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c<br>index a4b91e1..36f5c1d 100644<br>--- a/src/soc/intel/apollolake/pmc.c<br>+++ b/src/soc/intel/apollolake/pmc.c<br>@@ -1,7 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2016 Intel Corp.<br>+ * Copyright (C) 2016-2017 Intel Corp.<br> * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br> *<br> * This program is free software; you can redistribute it and/or modify<br>@@ -15,74 +15,25 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include "chip.h"<br>+#include <console/console.h><br> #include <device/device.h><br> #include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <console/console.h><br>-#include <cpu/x86/smm.h><br>+#include <intelblocks/pmc.h><br> #include <intelblocks/pmclib.h><br> #include <soc/iomap.h><br>-#include <soc/gpio.h><br>-#include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <timer.h><br>-#include "chip.h"<br> <br>-/*<br>- * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases<br>- * where the BAR reads back as 0, but the IO window is open. This also means<br>- * that it will not respond to PCI probing. In the event that probing the BAR<br>- * fails, we still need to create a resource for it.<br>- */<br>-static void read_resources(device_t dev)<br>+/* Fill up PMC resource structure */<br>+void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg)<br> {<br>- struct resource *res;<br>- pci_dev_read_resources(dev);<br>-<br>- res = new_resource(dev, PCI_BASE_ADDRESS_0);<br>- res->base = PMC_BAR0;<br>- res->size = PMC_BAR0_SIZE;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, PCI_BASE_ADDRESS_4);<br>- res->base = ACPI_BASE_ADDRESS;<br>- res->size = ACPI_BASE_SIZE;<br>- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-/*<br>- * Part 2:<br>- * Resources are assigned, and no other device was given an IO resource to<br>- * overlap with our ACPI BAR. But because the resource is FIXED,<br>- * pci_dev_set_resources() will not store it for us. We need to do that<br>- * explicitly.<br>- */<br>-static void set_resources(device_t dev)<br>-{<br>- struct resource *res;<br>-<br>- pci_dev_set_resources(dev);<br>-<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- pci_write_config32(dev, res->index, res->base);<br>- dev->command |= PCI_COMMAND_MEMORY;<br>- res->flags |= IORESOURCE_STORED;<br>- report_resource_stored(dev, res, " PMC BAR");<br>-<br>- res = find_resource(dev, PCI_BASE_ADDRESS_4);<br>- pci_write_config32(dev, res->index, res->base);<br>- dev->command |= PCI_COMMAND_IO;<br>- res->flags |= IORESOURCE_STORED;<br>- report_resource_stored(dev, res, " ACPI BAR");<br>-}<br>-<br>-static void pch_set_acpi_mode(void)<br>-{<br>- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {<br>- printk(BIOS_DEBUG, "Disabling ACPI via APMC:");<br>- outb(APM_CNT_ACPI_DISABLE, APM_CNT);<br>- printk(BIOS_DEBUG, "Done.\n");<br>- }<br>+ cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;<br>+ cfg->pwrmbase_addr = PMC_BAR0;<br>+ cfg->pwrmbase_size = PMC_BAR0_SIZE;<br>+ cfg->abase_offset = PCI_BASE_ADDRESS_4;<br>+ cfg->abase_addr = ACPI_BASE_ADDRESS;<br>+ cfg->abase_size = ACPI_BASE_SIZE;<br> }<br> <br> static int choose_slp_s3_assertion_width(int width_usecs)<br>@@ -138,14 +89,14 @@<br> write32((void *)gen_pmcon3, reg);<br> }<br> <br>-static void pmc_init(struct device *dev)<br>+void pmc_init(struct device *dev)<br> {<br> const struct soc_intel_apollolake_config *cfg = dev->chip_info;<br> <br> /* Set up GPE configuration */<br> pmc_gpe_init();<br> pmc_fixup_power_state();<br>- pch_set_acpi_mode();<br>+ pmc_set_acpi_mode();<br> <br> if (cfg != NULL)<br> set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);<br>@@ -156,22 +107,3 @@<br> /* Now that things have been logged clear out the PMC state. */<br> pmc_clear_prsts();<br> }<br>-<br>-static const struct device_operations device_ops = {<br>- .read_resources = read_resources,<br>- .set_resources = set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = &pmc_init,<br>-};<br>-<br>-static const unsigned short pci_device_ids[] = {<br>- PCI_DEVICE_ID_INTEL_APL_PMC,<br>- PCI_DEVICE_ID_INTEL_GLK_PMC,<br>- 0,<br>-};<br>-<br>-static const struct pci_driver pmc __pci_driver = {<br>- .ops = &device_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .devices= pci_device_ids,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22564">change 22564</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I968c88ef805fe58751f5359e27cbdf4d3fba3ae9 </div>
<div style="display:none"> Gerrit-Change-Number: 22564 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>