<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22526">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Constify struct cpu_device_id instances<br><br>There is currently no case where a struct cpu_device_id instance needs<br>to be modified. Thus, declare all instances as const.<br><br>Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/arch/arm/include/armv7/arch/cpu.h<br>M src/arch/mips/include/arch/cpu.h<br>M src/arch/power8/include/arch/cpu.h<br>M src/arch/riscv/include/arch/cpu.h<br>M src/arch/x86/cpu.c<br>M src/arch/x86/include/arch/cpu.h<br>M src/cpu/amd/agesa/family12/model_12_init.c<br>M src/cpu/amd/agesa/family14/model_14_init.c<br>M src/cpu/amd/agesa/family15/model_15_init.c<br>M src/cpu/amd/agesa/family15tn/model_15_init.c<br>M src/cpu/amd/agesa/family16kb/model_16_init.c<br>M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>M src/cpu/amd/geode_gx2/geode_gx2_init.c<br>M src/cpu/amd/geode_lx/geode_lx_init.c<br>M src/cpu/amd/model_fxx/model_fxx_init.c<br>M src/cpu/amd/pi/00630F01/model_15_init.c<br>M src/cpu/amd/pi/00660F01/model_15_init.c<br>M src/cpu/amd/pi/00730F01/model_16_init.c<br>M src/cpu/intel/ep80579/ep80579_init.c<br>M src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>M src/cpu/intel/fsp_model_406dx/model_406dx_init.c<br>M src/cpu/intel/haswell/haswell_init.c<br>M src/cpu/intel/model_1067x/model_1067x_init.c<br>M src/cpu/intel/model_106cx/model_106cx_init.c<br>M src/cpu/intel/model_2065x/model_2065x_init.c<br>M src/cpu/intel/model_206ax/model_206ax_init.c<br>M src/cpu/intel/model_65x/model_65x_init.c<br>M src/cpu/intel/model_67x/model_67x_init.c<br>M src/cpu/intel/model_68x/model_68x_init.c<br>M src/cpu/intel/model_69x/model_69x_init.c<br>M src/cpu/intel/model_6bx/model_6bx_init.c<br>M src/cpu/intel/model_6dx/model_6dx_init.c<br>M src/cpu/intel/model_6ex/model_6ex_init.c<br>M src/cpu/intel/model_6fx/model_6fx_init.c<br>M src/cpu/intel/model_6xx/model_6xx_init.c<br>M src/cpu/intel/model_f0x/model_f0x_init.c<br>M src/cpu/intel/model_f1x/model_f1x_init.c<br>M src/cpu/intel/model_f2x/model_f2x_init.c<br>M src/cpu/intel/model_f3x/model_f3x_init.c<br>M src/cpu/intel/model_f4x/model_f4x_init.c<br>M src/cpu/qemu-power8/qemu.c<br>M src/cpu/qemu-x86/qemu.c<br>M src/cpu/via/c3/c3_init.c<br>M src/cpu/via/c7/c7_init.c<br>M src/cpu/via/nano/nano_init.c<br>M src/soc/amd/stoneyridge/model_15_init.c<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/baytrail/cpu.c<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/common/block/cpu/mp_init.c<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/fsp_baytrail/cpu.c<br>M src/soc/intel/fsp_broadwell_de/cpu.c<br>54 files changed, 54 insertions(+), 54 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/22526/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h<br>index b7ef20d..18d86e0 100644<br>--- a/src/arch/arm/include/armv7/arch/cpu.h<br>+++ b/src/arch/arm/include/armv7/arch/cpu.h<br>@@ -25,7 +25,7 @@<br> <br> struct cpu_driver {<br> struct device_operations *ops;<br>- struct cpu_device_id *id_table;<br>+ const struct cpu_device_id *id_table;<br> };<br> <br> struct thread;<br>diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h<br>index d43fd62..f9f6197 100644<br>--- a/src/arch/mips/include/arch/cpu.h<br>+++ b/src/arch/mips/include/arch/cpu.h<br>@@ -24,7 +24,7 @@<br> <br> struct cpu_driver {<br> struct device_operations *ops;<br>- struct cpu_device_id *id_table;<br>+ const struct cpu_device_id *id_table;<br> };<br> <br> struct thread;<br>diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/power8/include/arch/cpu.h<br>index 9acc2a8..e0fb72c 100644<br>--- a/src/arch/power8/include/arch/cpu.h<br>+++ b/src/arch/power8/include/arch/cpu.h<br>@@ -23,7 +23,7 @@<br> <br> struct cpu_driver {<br> struct device_operations *ops;<br>- struct cpu_device_id *id_table;<br>+ const struct cpu_device_id *id_table;<br> };<br> <br> struct thread;<br>diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h<br>index ae5cbda..a0ca3ce 100644<br>--- a/src/arch/riscv/include/arch/cpu.h<br>+++ b/src/arch/riscv/include/arch/cpu.h<br>@@ -23,7 +23,7 @@<br> <br> struct cpu_driver {<br> struct device_operations *ops;<br>- struct cpu_device_id *id_table;<br>+ const struct cpu_device_id *id_table;<br> };<br> <br> struct thread;<br>diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c<br>index ff82661..cfcfdbd 100644<br>--- a/src/arch/x86/cpu.c<br>+++ b/src/arch/x86/cpu.c<br>@@ -203,7 +203,7 @@<br> {<br> struct cpu_driver *driver;<br> for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {<br>- struct cpu_device_id *id;<br>+ const struct cpu_device_id *id;<br> for (id = driver->id_table;<br> id->vendor != X86_VENDOR_INVALID; id++) {<br> if ((cpu->vendor == id->vendor) &&<br>diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h<br>index 1cba0af..5d44aae 100644<br>--- a/src/arch/x86/include/arch/cpu.h<br>+++ b/src/arch/x86/include/arch/cpu.h<br>@@ -178,7 +178,7 @@<br> <br> struct cpu_driver {<br> struct device_operations *ops;<br>- struct cpu_device_id *id_table;<br>+ const struct cpu_device_id *id_table;<br> struct acpi_cstate *cstates;<br> };<br> <br>diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c<br>index e533017..1d414a2 100644<br>--- a/src/cpu/amd/agesa/family12/model_12_init.c<br>+++ b/src/cpu/amd/agesa/family12/model_12_init.c<br>@@ -98,7 +98,7 @@<br> .init = model_12_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */<br> { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */<br> { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */<br>diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c<br>index 2cfb909..a03516d 100644<br>--- a/src/cpu/amd/agesa/family14/model_14_init.c<br>+++ b/src/cpu/amd/agesa/family14/model_14_init.c<br>@@ -116,7 +116,7 @@<br> .init = model_14_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */<br> { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */<br> { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */<br>diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c<br>index 7df9153..531bf29 100644<br>--- a/src/cpu/amd/agesa/family15/model_15_init.c<br>+++ b/src/cpu/amd/agesa/family15/model_15_init.c<br>@@ -101,7 +101,7 @@<br> .init = model_15_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */<br> { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */<br> { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */<br>diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c<br>index f569de7..e0bff4f 100644<br>--- a/src/cpu/amd/agesa/family15tn/model_15_init.c<br>+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c<br>@@ -128,7 +128,7 @@<br> .init = model_15_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */<br> { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */<br> { 0, 0 },<br>diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c<br>index acfa3f2..d49216a 100644<br>--- a/src/cpu/amd/agesa/family16kb/model_16_init.c<br>+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c<br>@@ -112,7 +112,7 @@<br> .init = model_16_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */<br> { 0, 0 },<br> };<br>diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>index 1e2a467..f73ce03 100644<br>--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>@@ -240,7 +240,7 @@<br> .init = model_10xxx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> //AMD_GH_SUPPORT<br> { X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */<br> { X86_VENDOR_AMD, 0x100f10 }, /* M2 */<br>diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c<br>index 2aa9c8d..6be3925 100644<br>--- a/src/cpu/amd/geode_gx2/geode_gx2_init.c<br>+++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c<br>@@ -47,7 +47,7 @@<br> .init = geode_gx2_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_NSC, 0x0552 },<br> { 0, 0 },<br> };<br>diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c<br>index 8ff5848..8c0cef3 100644<br>--- a/src/cpu/amd/geode_lx/geode_lx_init.c<br>+++ b/src/cpu/amd/geode_lx/geode_lx_init.c<br>@@ -58,7 +58,7 @@<br> .init = geode_lx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> {X86_VENDOR_AMD, 0x05A2},<br> {0, 0},<br> };<br>diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c<br>index c21bce6..f5a6773 100644<br>--- a/src/cpu/amd/model_fxx/model_fxx_init.c<br>+++ b/src/cpu/amd/model_fxx/model_fxx_init.c<br>@@ -558,7 +558,7 @@<br> .init = model_fxx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */<br> { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */<br>diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c<br>index 317aca8..5299dca 100644<br>--- a/src/cpu/amd/pi/00630F01/model_15_init.c<br>+++ b/src/cpu/amd/pi/00630F01/model_15_init.c<br>@@ -124,7 +124,7 @@<br> .init = model_15_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x630f00 }, /* KV-A0 */<br> { X86_VENDOR_AMD, 0x630f01 }, /* KV-A1 */<br> { 0, 0 },<br>diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c<br>index bf4bc24..abe20c3 100644<br>--- a/src/cpu/amd/pi/00660F01/model_15_init.c<br>+++ b/src/cpu/amd/pi/00660F01/model_15_init.c<br>@@ -124,7 +124,7 @@<br> .init = model_15_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x660f00 },<br> { X86_VENDOR_AMD, 0x660f01 },<br> { 0, 0 },<br>diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c<br>index 0dd7202..e0eca94 100644<br>--- a/src/cpu/amd/pi/00730F01/model_16_init.c<br>+++ b/src/cpu/amd/pi/00730F01/model_16_init.c<br>@@ -108,7 +108,7 @@<br> .init = model_16_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x730F00 },<br> { X86_VENDOR_AMD, 0x730F01 },<br> { 0, 0 },<br>diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c<br>index 78860b4..d19d4e2 100644<br>--- a/src/cpu/intel/ep80579/ep80579_init.c<br>+++ b/src/cpu/intel/ep80579/ep80579_init.c<br>@@ -42,7 +42,7 @@<br> .init = ep80579_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */<br> { 0, 0 },<br> };<br>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>index 30a8d15..3eb07b0 100644<br>--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>@@ -375,7 +375,7 @@<br> .init = model_206ax_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */<br> { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */<br> { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */<br>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c<br>index ab3b6b3..289305f 100644<br>--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c<br>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c<br>@@ -161,7 +161,7 @@<br> .init = model_406dx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x406d0 }, /* Intel Avoton/Rangeley A1 */<br> { X86_VENDOR_INTEL, 0x406d8 }, /* Intel Avoton/Rangeley B0 */<br> { 0, 0 },<br>diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c<br>index aa7711b..24de43e 100644<br>--- a/src/cpu/intel/haswell/haswell_init.c<br>+++ b/src/cpu/intel/haswell/haswell_init.c<br>@@ -789,7 +789,7 @@<br> .init = haswell_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */<br> { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */<br> { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */<br>diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c<br>index 01cb45d..0d9169b 100644<br>--- a/src/cpu/intel/model_1067x/model_1067x_init.c<br>+++ b/src/cpu/intel/model_1067x/model_1067x_init.c<br>@@ -322,7 +322,7 @@<br> .init = model_1067x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */<br> { X86_VENDOR_INTEL, 0x10677 },<br> { X86_VENDOR_INTEL, 0x1067A },<br>diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c<br>index b07fd0b..dd7bbc8 100644<br>--- a/src/cpu/intel/model_106cx/model_106cx_init.c<br>+++ b/src/cpu/intel/model_106cx/model_106cx_init.c<br>@@ -118,7 +118,7 @@<br> .init = model_106cx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */<br> { X86_VENDOR_INTEL, 0x106ca }, /* Intel Atom D5xx */<br> { 0, 0 },<br>diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c<br>index 377e297..322e814 100644<br>--- a/src/cpu/intel/model_2065x/model_2065x_init.c<br>+++ b/src/cpu/intel/model_2065x/model_2065x_init.c<br>@@ -359,7 +359,7 @@<br> .init = model_2065x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x20652 }, /* Intel Nehalem */<br> { X86_VENDOR_INTEL, 0x20655 }, /* Intel Nehalem */<br> { 0, 0 },<br>diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c<br>index ed5c292..5c60ed7 100644<br>--- a/src/cpu/intel/model_206ax/model_206ax_init.c<br>+++ b/src/cpu/intel/model_206ax/model_206ax_init.c<br>@@ -557,7 +557,7 @@<br> .init = model_206ax_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */<br> { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */<br> { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */<br>diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c<br>index a4e222d..9eab9c7 100644<br>--- a/src/cpu/intel/model_65x/model_65x_init.c<br>+++ b/src/cpu/intel/model_65x/model_65x_init.c<br>@@ -54,7 +54,7 @@<br> * Intel Pentium II Xeon Processor Specification Update<br> * http://download.intel.com/support/processors/pentiumii/xeon/24377632.pdf<br> */<br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */<br> { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */<br> { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */<br>diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c<br>index f4b8155..4fd51d3 100644<br>--- a/src/cpu/intel/model_67x/model_67x_init.c<br>+++ b/src/cpu/intel/model_67x/model_67x_init.c<br>@@ -55,7 +55,7 @@<br> * Intel Pentium III Processor Specification Update<br> * http://download.intel.com/design/intarch/specupdt/24445358.pdf<br> */<br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0671 },<br> { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */<br> { X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */<br>diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c<br>index ad1f3a0..17c9eb7 100644<br>--- a/src/cpu/intel/model_68x/model_68x_init.c<br>+++ b/src/cpu/intel/model_68x/model_68x_init.c<br>@@ -65,7 +65,7 @@<br> * Mobile Intel Pentium III/III-M Processor Specification Update<br> * http://download.intel.com/design/intarch/specupdt/24530663.pdf<br> */<br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0680 },<br> { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */<br> { X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/<br>diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c<br>index ba0af24..785c480 100644<br>--- a/src/cpu/intel/model_69x/model_69x_init.c<br>+++ b/src/cpu/intel/model_69x/model_69x_init.c<br>@@ -39,7 +39,7 @@<br> .init = model_69x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */<br> { X86_VENDOR_INTEL, 0x0695 },<br> { 0, 0 },<br>diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c<br>index e52bd31..ce70539 100644<br>--- a/src/cpu/intel/model_6bx/model_6bx_init.c<br>+++ b/src/cpu/intel/model_6bx/model_6bx_init.c<br>@@ -59,7 +59,7 @@<br> * Intel Pentium III Processor Specification Update<br> * http://download.intel.com/design/intarch/specupdt/24445358.pdf<br> */<br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */<br> { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */<br> { 0, 0 },<br>diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c<br>index 0a51914..6097c33 100644<br>--- a/src/cpu/intel/model_6dx/model_6dx_init.c<br>+++ b/src/cpu/intel/model_6dx/model_6dx_init.c<br>@@ -39,7 +39,7 @@<br> .init = model_6dx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> /* Pentium M on 90nm with 2MiB of L2 cache */<br> { X86_VENDOR_INTEL, 0x06D0 },<br> { X86_VENDOR_INTEL, 0x06D6 },<br>diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c<br>index ff9284f..6e5b339 100644<br>--- a/src/cpu/intel/model_6ex/model_6ex_init.c<br>+++ b/src/cpu/intel/model_6ex/model_6ex_init.c<br>@@ -156,7 +156,7 @@<br> .init = model_6ex_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */<br> { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */<br> { X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */<br>diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c<br>index 2a04a4e..b5a68cc 100644<br>--- a/src/cpu/intel/model_6fx/model_6fx_init.c<br>+++ b/src/cpu/intel/model_6fx/model_6fx_init.c<br>@@ -170,7 +170,7 @@<br> .init = model_6fx_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */<br> { X86_VENDOR_INTEL, 0x06f2 }, /* Intel Core 2 Solo/Core Duo */<br> { X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */<br>diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c<br>index 68c0136..e639ed7 100644<br>--- a/src/cpu/intel/model_6xx/model_6xx_init.c<br>+++ b/src/cpu/intel/model_6xx/model_6xx_init.c<br>@@ -64,7 +64,7 @@<br> * Mobile Intel Pentium III/III-M Processor Specification Update<br> * http://download.intel.com/design/intarch/specupdt/24530663.pdf<br> */<br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0611 }, /* Pentium Pro, B0 */<br> { X86_VENDOR_INTEL, 0x0612 }, /* Pentium Pro, C0 */<br> { X86_VENDOR_INTEL, 0x0616 }, /* Pentium Pro, sA0 */<br>diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c<br>index f833a56..d942445d 100644<br>--- a/src/cpu/intel/model_f0x/model_f0x_init.c<br>+++ b/src/cpu/intel/model_f0x/model_f0x_init.c<br>@@ -39,7 +39,7 @@<br> .init = model_f0x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0f07 },<br> { X86_VENDOR_INTEL, 0x0f0A },<br> { 0, 0 },<br>diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c<br>index 4af3934..e0ef3fe 100644<br>--- a/src/cpu/intel/model_f1x/model_f1x_init.c<br>+++ b/src/cpu/intel/model_f1x/model_f1x_init.c<br>@@ -39,7 +39,7 @@<br> .init = model_f1x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0f12 },<br> { X86_VENDOR_INTEL, 0x0f13 },<br> { 0, 0 },<br>diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c<br>index 97c7d9d..03377d8 100644<br>--- a/src/cpu/intel/model_f2x/model_f2x_init.c<br>+++ b/src/cpu/intel/model_f2x/model_f2x_init.c<br>@@ -47,7 +47,7 @@<br> .init = model_f2x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0f22 },<br> { X86_VENDOR_INTEL, 0x0f24 },<br> { X86_VENDOR_INTEL, 0x0f25 },<br>diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c<br>index 8fbcaa7..d853a63 100644<br>--- a/src/cpu/intel/model_f3x/model_f3x_init.c<br>+++ b/src/cpu/intel/model_f3x/model_f3x_init.c<br>@@ -47,7 +47,7 @@<br> .init = model_f3x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0f34 }, /* Xeon */<br> { 0, 0 },<br> };<br>diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c<br>index c904b62..9eb5115 100644<br>--- a/src/cpu/intel/model_f4x/model_f4x_init.c<br>+++ b/src/cpu/intel/model_f4x/model_f4x_init.c<br>@@ -47,7 +47,7 @@<br> .init = model_f4x_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x0f41 }, /* Xeon */<br> { 0, 0 },<br> };<br>diff --git a/src/cpu/qemu-power8/qemu.c b/src/cpu/qemu-power8/qemu.c<br>index 5518a27..826624a 100644<br>--- a/src/cpu/qemu-power8/qemu.c<br>+++ b/src/cpu/qemu-power8/qemu.c<br>@@ -23,7 +23,7 @@<br> .init = qemu_cpu_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { 0, 0 },<br> };<br> <br>diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c<br>index 924c2fd..c005bf7 100644<br>--- a/src/cpu/qemu-x86/qemu.c<br>+++ b/src/cpu/qemu-x86/qemu.c<br>@@ -25,7 +25,7 @@<br> .init = qemu_cpu_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_ANY, 0 },<br> { 0, 0 },<br> };<br>diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c<br>index e51c0d6..353cbfa 100644<br>--- a/src/cpu/via/c3/c3_init.c<br>+++ b/src/cpu/via/c3/c3_init.c<br>@@ -35,7 +35,7 @@<br> .init = c3_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_CENTAUR, 0x0670 }, // VIA C3 Samual 2 + Ezra<br> { X86_VENDOR_CENTAUR, 0x0680 }, // VIA C3 Ezra-T<br> { X86_VENDOR_CENTAUR, 0x0690 }, // VIA C3 Nehemiah<br>diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c<br>index 480f61a..1527e64 100644<br>--- a/src/cpu/via/c7/c7_init.c<br>+++ b/src/cpu/via/c7/c7_init.c<br>@@ -213,7 +213,7 @@<br> * allows us to keep the table significantly smaller.<br> */<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> {X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther<br> {X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther<br> {X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M<br>diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c<br>index 7d6338e..62c6316 100644<br>--- a/src/cpu/via/nano/nano_init.c<br>+++ b/src/cpu/via/nano/nano_init.c<br>@@ -188,7 +188,7 @@<br> .init = nano_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series<br> {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0<br> {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2<br>diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c<br>index c3e9bf5..930e395 100644<br>--- a/src/soc/amd/stoneyridge/model_15_init.c<br>+++ b/src/soc/amd/stoneyridge/model_15_init.c<br>@@ -87,7 +87,7 @@<br> .init = model_15_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_AMD, 0x670f00 },<br> { 0, 0 },<br> };<br>diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c<br>index d2c7001..96c37f1 100644<br>--- a/src/soc/intel/apollolake/cpu.c<br>+++ b/src/soc/intel/apollolake/cpu.c<br>@@ -103,7 +103,7 @@<br> .init = soc_init_core,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },<br> { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },<br> { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 },<br>diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c<br>index a384404..ed18ce1 100644<br>--- a/src/soc/intel/baytrail/cpu.c<br>+++ b/src/soc/intel/baytrail/cpu.c<br>@@ -66,7 +66,7 @@<br> .init = baytrail_core_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x30673 },<br> { X86_VENDOR_INTEL, 0x30678 },<br> { 0, 0 },<br>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c<br>index a2bd180..ed7e2fa 100644<br>--- a/src/soc/intel/braswell/cpu.c<br>+++ b/src/soc/intel/braswell/cpu.c<br>@@ -71,7 +71,7 @@<br> .init = soc_core_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x406C4 },<br> { X86_VENDOR_INTEL, 0x406C3 },<br> { X86_VENDOR_INTEL, 0x406C2 },<br>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c<br>index 7b56db1..ecb7247 100644<br>--- a/src/soc/intel/broadwell/cpu.c<br>+++ b/src/soc/intel/broadwell/cpu.c<br>@@ -684,7 +684,7 @@<br> .init = cpu_core_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, CPUID_HASWELL_ULT },<br> { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 },<br> { X86_VENDOR_INTEL, CPUID_BROADWELL_D0 },<br>diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c<br>index e301c24..e19127c 100644<br>--- a/src/soc/intel/common/block/cpu/mp_init.c<br>+++ b/src/soc/intel/common/block/cpu/mp_init.c<br>@@ -50,7 +50,7 @@<br> .init = init_one_cpu,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 },<br> { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },<br> { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 },<br>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c<br>index b6c05e7..528d2e5 100644<br>--- a/src/soc/intel/denverton_ns/cpu.c<br>+++ b/src/soc/intel/denverton_ns/cpu.c<br>@@ -54,7 +54,7 @@<br> .init = denverton_core_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> {X86_VENDOR_INTEL,<br> CPUID_DENVERTON_A0_A1}, /* Denverton-NS A0/A1 CPUID */<br> {X86_VENDOR_INTEL, CPUID_DENVERTON_B0}, /* Denverton-NS B0 CPUID */<br>diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c<br>index c3879e1..38c4446 100644<br>--- a/src/soc/intel/fsp_baytrail/cpu.c<br>+++ b/src/soc/intel/fsp_baytrail/cpu.c<br>@@ -64,7 +64,7 @@<br> .init = baytrail_core_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x30671 },<br> { X86_VENDOR_INTEL, 0x30672 },<br> { X86_VENDOR_INTEL, 0x30673 },<br>diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c<br>index 68825a3..d89ae87 100644<br>--- a/src/soc/intel/fsp_broadwell_de/cpu.c<br>+++ b/src/soc/intel/fsp_broadwell_de/cpu.c<br>@@ -160,7 +160,7 @@<br> .init = broadwell_de_core_init,<br> };<br> <br>-static struct cpu_device_id cpu_table[] = {<br>+static const struct cpu_device_id cpu_table[] = {<br> { X86_VENDOR_INTEL, 0x50661 },<br> { X86_VENDOR_INTEL, 0x50662 },<br> { X86_VENDOR_INTEL, 0x50663 },<br></pre><p>To view, visit <a href="https://review.coreboot.org/22526">change 22526</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22526"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 </div>
<div style="display:none"> Gerrit-Change-Number: 22526 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>