<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22545">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Create soc.asl<br><br>Request from commit 519680948b466d786c618286ac1e8baa9cc6e22c, merge<br>several includes into a single file in soc directory.<br><br>To match comment, rename soc_fch.asl to southbridge.asl. Then copy<br>the required section from dsdt.asl into a new soc.asl.<br><br>Affected boards: amd/gardenia and google/kahlee.<br><br>BUG=b:69368752<br><br>Change-Id: Ib6b610e11d25d1d0fcf10e7d60a32559bc835a54<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/amd/gardenia/dsdt.asl<br>M src/mainboard/google/kahlee/dsdt.asl<br>A src/soc/amd/stoneyridge/acpi/soc.asl<br>R src/soc/amd/stoneyridge/acpi/southbridge.asl<br>4 files changed, 34 insertions(+), 28 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22545/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl<br>index bc81602..2800fe7 100644<br>--- a/src/mainboard/amd/gardenia/dsdt.asl<br>+++ b/src/mainboard/amd/gardenia/dsdt.asl<br>@@ -1,7 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -61,19 +61,8 @@<br> Name(_STA, 0x0B)<br> }<br> <br>- Device(PCI0) {<br>- /* Describe the AMD Northbridge */<br>- #include <northbridge.asl><br>-<br>- /* Describe the AMD Fusion Controller Hub Southbridge */<br>- #include <fch.asl><br>- }<br>-<br>- /* Describe PCI INT[A-H] for the Southbridge */<br>- #include <pci_int.asl><br>-<br>- /* Describe the devices in the Southbridge */<br>- #include <soc_fch.asl><br>+ /* describe the soc */<br>+ #include <soc.asl><br> <br> } /* End \_SB scope */<br> <br>diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl<br>index 885dd8d..fa0f520 100644<br>--- a/src/mainboard/google/kahlee/dsdt.asl<br>+++ b/src/mainboard/google/kahlee/dsdt.asl<br>@@ -1,7 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -61,19 +61,8 @@<br> Name(_UID, 0xAA)<br> }<br> <br>- Device(PCI0) {<br>- /* Describe the AMD Northbridge */<br>- #include <northbridge.asl><br>-<br>- /* Describe the AMD Fusion Controller Hub Southbridge */<br>- #include <fch.asl><br>- }<br>-<br>- /* Describe PCI INT[A-H] for the Southbridge */<br>- #include <pci_int.asl><br>-<br>- /* Describe the devices in the Southbridge */<br>- #include <soc_fch.asl><br>+ /* describe the soc */<br>+ #include <soc.asl><br> <br> } /* End \_SB scope */<br> <br>diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl<br>new file mode 100644<br>index 0000000..a961f01<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/acpi/soc.asl<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Device(PCI0) {<br>+ /* Describe the AMD Northbridge */<br>+ #include "northbridge.asl"<br>+<br>+ /* Describe the AMD Fusion Controller Hub Southbridge */<br>+ #include "fch.asl"<br>+}<br>+<br>+/* Describe PCI INT[A-H] for the Southbridge */<br>+#include "pci_int.asl"<br>+<br>+/* Describe the devices in the Southbridge */<br>+#include "southbridge.asl"<br>diff --git a/src/soc/amd/stoneyridge/acpi/soc_fch.asl b/src/soc/amd/stoneyridge/acpi/southbridge.asl<br>similarity index 100%<br>rename from src/soc/amd/stoneyridge/acpi/soc_fch.asl<br>rename to src/soc/amd/stoneyridge/acpi/southbridge.asl<br></pre><p>To view, visit <a href="https://review.coreboot.org/22545">change 22545</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib6b610e11d25d1d0fcf10e7d60a32559bc835a54 </div>
<div style="display:none"> Gerrit-Change-Number: 22545 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>