<p>Vaibhav Shankar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22487">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add PM methods to power gate SD card controller<br><br>When system enters S0ix, system fails to power gate SD card<br>controller.<br><br>This patch implements PM methods put the SD card controller<br>in D3 during S0ix entry.<br><br>TEST=Suspend and resume using 'echo freeze > /sys/power/state'.<br>The System should not be blocked by sd card controller.<br><br>Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445<br>Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com><br>---<br>M src/soc/intel/cannonlake/acpi/scs.asl<br>1 file changed, 23 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22487/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl<br>index ed695fd..7620cb7 100644<br>--- a/src/soc/intel/cannonlake/acpi/scs.asl<br>+++ b/src/soc/intel/cannonlake/acpi/scs.asl<br>@@ -40,5 +40,28 @@<br>     {<br>             Name (_ADR, 0x00140005)<br> <br>+           OperationRegion(SDPC, PCI_Config, 0x00, 0x100)<br>+               Field(SDPC, WordAcc, NoLock, Preserve)<br>+               {<br>+                    Offset(0x84),  /* PMCSR - Power Management<br>+                                     Control and Status */<br>+                      PMCR,32,<br>+                     Offset(0xA2),  /* Device Power Gate config */<br>+                        , 2,<br>+                 PGEN, 1 /* PGE - PG Enable */<br>+                }<br>+<br>+         Method(_PS0, 0, Serialized)<br>+          {<br>+                    Store(0, PGEN) /* Disable PG */<br>+                      And(PMCR, 0xFFFFFFFC, PMCR) /* Power State D0 */<br>+             }<br>+<br>+         Method(_PS3, 0, Serialized)<br>+          {<br>+<br>+                 Store(1, PGEN) /* Enable PG */<br>+                       Or(PMCR, 0x3, PMCR) /* Power State D3 */<br>+             }<br>     } /* Device (SDXC) */<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22487">change 22487</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22487"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445 </div>
<div style="display:none"> Gerrit-Change-Number: 22487 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar@intel.com> </div>