<p>Lin Huang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22469">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">rockchip/rk3399: improve mipi transfer flow<br><br>check GEN_CMD_FULL status before transfer, check<br>GEN_CMD_EMPTY and GEN_PLD_W_EMPTY status after<br>transfer.<br><br>Change-Id: I936c0d888b10f13141519f95ac7bcae3e15e95d9<br>Signed-off-by: Lin Huang <hl@rock-chips.com><br>---<br>M src/soc/rockchip/rk3399/include/soc/mipi.h<br>M src/soc/rockchip/rk3399/mipi.c<br>2 files changed, 72 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22469/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h<br>index d716717..3b0b00e 100644<br>--- a/src/soc/rockchip/rk3399/include/soc/mipi.h<br>+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h<br>@@ -243,6 +243,17 @@<br> #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22<br> #define HS_RX_CONTROL_OF_LANE_0 0x44<br> <br>+#define GEN_CMD_EMPTY BIT(0)<br>+#define GEN_CMD_FULL BIT(1)<br>+#define GEN_PLD_W_EMPTY BIT(2)<br>+#define GEN_PLD_W_FULL BIT(3)<br>+#define GEN_PLD_R_EMPTY BIT(4)<br>+#define GEN_PLD_R_FULL BIT(5)<br>+#define GEN_RD_CMD_BUSY BIT(6)<br>+<br>+#define MIPI_DSI_DCS_SHORT_WRITE 0x05<br>+#define MIPI_DSI_DCS_LONG_WRITE 0x39<br>+<br> enum mipi_dsi_pixel_format {<br> MIPI_DSI_FMT_RGB888,<br> MIPI_DSI_FMT_RGB666,<br>diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c<br>index 12e6608..e69eb49 100644<br>--- a/src/soc/rockchip/rk3399/mipi.c<br>+++ b/src/soc/rockchip/rk3399/mipi.c<br>@@ -460,26 +460,68 @@<br> TX_ESC_CLK_DIVIDSION(esc_clk_division));<br> }<br> <br>-static int rk_mipi_dsi_dcs_transfer(struct rk_mipi_dsi *dsi, u32 hdr_val)<br>+static void rk_mipi_message_config(struct rk_mipi_dsi *dsi)<br> {<br>- int ret;<br>-<br>- hdr_val = GEN_HDATA(hdr_val) | GEN_HTYPE(0x05);<br>- ret = read32(&mipi_regs->dsi_cmd_pkt_status);<br>- if (ret < 0) {<br>- printk(BIOS_DEBUG, "failed to get available command FIFO\n");<br>- return ret;<br>- }<br>-<br> write32(&mipi_regs->dsi_lpclk_ctrl, 0);<br> write32(&mipi_regs->dsi_cmd_mode_cfg, CMD_MODE_ALL_LP);<br>+}<br>+<br>+static int rk_mipi_dsi_check_cmd_fifo(struct rk_mipi_dsi *dsi)<br>+{<br>+ struct stopwatch sw;<br>+ int val;<br>+<br>+ stopwatch_init_msecs_expire(&sw, 20);<br>+ do {<br>+ val = read32(&mipi_regs->dsi_cmd_pkt_status);<br>+ if (!(val & GEN_CMD_FULL))<br>+ return 0 ;<br>+ } while (!stopwatch_expired(&sw));<br>+<br>+ return -1;<br>+}<br>+<br>+static int rk_mipi_dsi_gen_pkt_hdr_write(struct rk_mipi_dsi *dsi, u32 hdr_val)<br>+{<br>+ int val;<br>+ struct stopwatch sw;<br>+ u32 mask;<br>+<br>+ if (rk_mipi_dsi_check_cmd_fifo(dsi)) {<br>+ printk(BIOS_ERR, "failed to get available command FIFO\n");<br>+ return 1;<br>+ }<br>+<br> write32(&mipi_regs->dsi_gen_hdr, hdr_val);<br> <br>- return 0;<br>+ mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;<br>+ stopwatch_init_msecs_expire(&sw, 20);<br>+ do {<br>+ val = read32(&mipi_regs->dsi_cmd_pkt_status);<br>+ if ((val & mask) == mask)<br>+ return 0 ;<br>+ } while (!stopwatch_expired(&sw));<br>+ printk(BIOS_ERR, "failed to write command FIFO\n");<br>+<br>+ return -1;<br>+}<br>+<br>+static int rk_mipi_dsi_dcs_short_write(struct rk_mipi_dsi *dsi,<br>+ u16 data, u8 type)<br>+{<br>+ u32 val;<br>+<br>+ rk_mipi_message_config(dsi);<br>+<br>+ val = GEN_HDATA(data) | GEN_HTYPE(type);<br>+<br>+ return rk_mipi_dsi_gen_pkt_hdr_write(dsi, val);<br> }<br> <br> void rk_mipi_prepare(const struct edid *edid, u32 display_on_mdelay, u32 video_mode_mdelay)<br> {<br>+ u16 value;<br>+<br> rk_mipi.lanes = 4;<br> rk_mipi.format = MIPI_DSI_FMT_RGB888;<br> if (rk_mipi_dsi_get_lane_bps(&rk_mipi, edid) < 0)<br>@@ -501,10 +543,16 @@<br> rk_mipi_dsi_wait_for_two_frames(&rk_mipi, edid);<br> <br> rk_mipi_dsi_set_mode(&rk_mipi, MIPI_DSI_CMD_MODE);<br>- if (rk_mipi_dsi_dcs_transfer(&rk_mipi, MIPI_DCS_EXIT_SLEEP_MODE) < 0)<br>+<br>+ value = MIPI_DCS_EXIT_SLEEP_MODE;<br>+ if (rk_mipi_dsi_dcs_short_write(&rk_mipi,<br>+ value, MIPI_DSI_DCS_SHORT_WRITE) < 0)<br> return;<br> mdelay(display_on_mdelay);<br>- if (rk_mipi_dsi_dcs_transfer(&rk_mipi, MIPI_DCS_SET_DISPLAY_ON) < 0)<br>+<br>+ value = MIPI_DCS_SET_DISPLAY_ON;<br>+ if (rk_mipi_dsi_dcs_short_write(&rk_mipi,<br>+ value, MIPI_DSI_DCS_SHORT_WRITE) < 0)<br> return;<br> mdelay(video_mode_mdelay);<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22469">change 22469</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22469"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I936c0d888b10f13141519f95ac7bcae3e15e95d9 </div>
<div style="display:none"> Gerrit-Change-Number: 22469 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lin Huang <hl@rock-chips.com> </div>