<p>Lin Huang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22470">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">rockchip/rk3399: mipi: properly configure PHY timing<br><br>These values are specified as constant time periods but the PHY<br>configuration is in terms of the current lane byte clock so using<br>constant values guarantees that the timings will be outside the<br>specification with some display configurations.<br><br>Derive the necessary configuration from the byte clock in order to<br>ensure that the PHY configuration is correct.<br><br>Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd<br>Signed-off-by: Lin Huang <hl@rock-chips.com><br>---<br>M src/soc/rockchip/rk3399/include/soc/mipi.h<br>M src/soc/rockchip/rk3399/mipi.c<br>2 files changed, 88 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/22470/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h<br>index 3b0b00e..f427376 100644<br>--- a/src/soc/rockchip/rk3399/include/soc/mipi.h<br>+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h<br>@@ -232,16 +232,27 @@<br> #define THS_PRE_PROGRAM_EN BIT(7)<br> #define THS_ZERO_PROGRAM_EN BIT(6)<br> <br>-#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10<br>-#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11<br>-#define PLL_LPF_AND_CP_CONTROL 0x12<br>-#define PLL_INPUT_DIVIDER_RATIO 0x17<br>-#define PLL_LOOP_DIVIDER_RATIO 0x18<br>-#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19<br>-#define BANDGAP_AND_BIAS_CONTROL 0x20<br>-#define TERMINATION_RESISTER_CONTROL 0x21<br>-#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22<br>-#define HS_RX_CONTROL_OF_LANE_0 0x44<br>+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10<br>+#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11<br>+#define PLL_LPF_AND_CP_CONTROL 0x12<br>+#define PLL_INPUT_DIVIDER_RATIO 0x17<br>+#define PLL_LOOP_DIVIDER_RATIO 0x18<br>+#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19<br>+#define BANDGAP_AND_BIAS_CONTROL 0x20<br>+#define TERMINATION_RESISTER_CONTROL 0x21<br>+#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22<br>+#define HS_RX_CONTROL_OF_LANE_0 0x44<br>+#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60<br>+#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61<br>+#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62<br>+#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63<br>+#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64<br>+#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65<br>+#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70<br>+#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71<br>+#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72<br>+#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73<br>+#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74<br> <br> #define GEN_CMD_EMPTY BIT(0)<br> #define GEN_CMD_FULL BIT(1)<br>diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c<br>index e69eb49..f0a20c4 100644<br>--- a/src/soc/rockchip/rk3399/mipi.c<br>+++ b/src/soc/rockchip/rk3399/mipi.c<br>@@ -123,10 +123,38 @@<br> write32(&mipi_regs->dsi_phy_tst_ctrl0, PHY_TESTCLK | PHY_UNTESTCLR);<br> }<br> <br>+/* bytes_per_ns - Nanoseconds to byte clock cycles */<br>+static inline unsigned int bytes_per_ns(struct rk_mipi_dsi *dsi, int ns)<br>+{<br>+ return DIV_ROUND_UP((u64)ns * dsi->lane_bps, (u64)8 * NSECS_PER_SEC);<br>+}<br>+<br>+ /* bits_per_ns - Nanoseconds to bit time periods */<br>+static inline unsigned int bits_per_ns(struct rk_mipi_dsi *dsi, int ns)<br>+{<br>+ return DIV_ROUND_UP((u64)ns * dsi->lane_bps, NSECS_PER_SEC);<br>+}<br>+<br>+static int rk_mipi_dsi_wait_phy_lock(struct rk_mipi_dsi *dsi)<br>+{<br>+ struct stopwatch sw;<br>+ int val;<br>+<br>+ stopwatch_init_msecs_expire(&sw, 20);<br>+ do {<br>+ val = read32(&mipi_regs->dsi_phy_status);<br>+ if (val & LOCK)<br>+ return 0;<br>+ } while (!stopwatch_expired(&sw));<br>+<br>+ return -1;<br>+}<br>+<br> static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)<br> {<br>- int i, vco;<br>+ int i, vco, val;<br> int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);<br>+ struct stopwatch sw;<br> <br> vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;<br> <br>@@ -192,10 +220,47 @@<br> TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |<br> SETRD_MAX | POWER_MANAGE |<br> TER_RESISTORS_ON);<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,<br>+ TLP_PROGRAM_EN | bytes_per_ns(dsi, 500));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,<br>+ THS_PRE_PROGRAM_EN | bits_per_ns(dsi, 40));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,<br>+ THS_ZERO_PROGRAM_EN | bytes_per_ns(dsi, 300));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,<br>+ THS_PRE_PROGRAM_EN | bits_per_ns(dsi, 100));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,<br>+ BIT(5) | bytes_per_ns(dsi, 100));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,<br>+ BIT(5) | (bytes_per_ns(dsi, 60) + 7));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,<br>+ TLP_PROGRAM_EN | bytes_per_ns(dsi, 500));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,<br>+ THS_PRE_PROGRAM_EN | (bits_per_ns(dsi, 50) + 5));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,<br>+ THS_ZERO_PROGRAM_EN |<br>+ (bytes_per_ns(dsi, 140) + 2));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,<br>+ THS_PRE_PROGRAM_EN | (bits_per_ns(dsi, 60) + 8));<br>+ rk_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,<br>+ BIT(5) | bytes_per_ns(dsi, 100));<br> <br> write32(&mipi_regs->dsi_phy_rstz, PHY_ENFORCEPLL | PHY_ENABLECLK |<br> PHY_UNRSTZ | PHY_UNSHUTDOWNZ);<br>- return 0;<br>+<br>+ if (rk_mipi_dsi_wait_phy_lock(dsi)) {<br>+ printk(BIOS_ERR, "failed to wait for phy lock state\n");<br>+ return -1;<br>+ }<br>+<br>+ stopwatch_init_msecs_expire(&sw, 20);<br>+ do {<br>+ val = read32(&mipi_regs->dsi_phy_status);<br>+ if (val & STOP_STATE_CLK_LANE)<br>+ return 0;<br>+ } while (!stopwatch_expired(&sw));<br>+<br>+ printk(BIOS_ERR, "failed to wait for phy clk lane stop state");<br>+ return -1;<br> }<br> <br> static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22470">change 22470</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd </div>
<div style="display:none"> Gerrit-Change-Number: 22470 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lin Huang <hl@rock-chips.com> </div>