<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22473">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">asus/p2b: Align ACPI tables with asus/p2b-ls<br><br>Updates ACPI tables with work done for asus/p2b-ls, including super I/O<br>related declarations.<br><br>Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/mainboard/asus/p2b/dsdt.asl<br>1 file changed, 153 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/22473/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl<br>index 00bea29..5ef6bdb 100644<br>--- a/src/mainboard/asus/p2b/dsdt.asl<br>+++ b/src/mainboard/asus/p2b/dsdt.asl<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -15,8 +16,29 @@<br> <br> #include "southbridge/intel/i82371eb/i82371eb.h"<br> <br>+#define SUPERIO_PNP_BASE 0x3F0<br>+#define SUPERIO_SHOW_UARTA<br>+#define SUPERIO_SHOW_UARTB<br>+#define SUPERIO_SHOW_FDC<br>+#define SUPERIO_SHOW_LPT<br>+<br> DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)<br> {<br>+ /* \_PR scope defining the main processor is generated in SSDT. */<br>+<br>+ OperationRegion(X80, SystemIO, 0x80, 1)<br>+ Field(X80, ByteAcc, NoLock, Preserve)<br>+ {<br>+ P80, 8<br>+ }<br>+<br>+ /*<br>+ * For now only define 2 power states:<br>+ * - S0 which is fully on<br>+ * - S5 which is soft off<br>+ * Any others would involve declaring the wake up methods.<br>+ */<br>+<br> /*<br> * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142<br> *<br>@@ -38,25 +60,41 @@<br> Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })<br> Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })<br> <br>- OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)<br>- Field (SIO1, ByteAcc, NoLock, Preserve)<br>+ OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10)<br>+ Field (GPOB, ByteAcc, NoLock, Preserve)<br> {<br>- FANP, 1, /* CPU/case fan power */<br>- Offset (0x01),<br>- PLED, 1,<br>+ Offset (0x03),<br>+ TO12, 1, /* Device trap 12 */<br>+ Offset (0x08),<br>+ FANM, 1, /* GPO0, meant for fan */<br>+ Offset (0x09),<br>+ PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */<br>+ , 3, /* this goes low when power is cut from its core. */<br>+ , 2,<br>+ , 16,<br>+ MSG0, 1 /* GPO30, message LED */<br> }<br> <br>+ /* Prepare To Sleep, Arg0 is target S-state */<br> Method (\_PTS, 1, NotSerialized)<br> {<br>- /* Disable fan, blink power led */<br>- Store (Zero, FANP)<br>- Store (Zero, PLED)<br>+ /* Disable fan, blink power LED, if not turning off */<br>+ If (LNotEqual (Arg0, 0x05))<br>+ {<br>+ Store (Zero, FANM)<br>+ Store (Zero, PLED)<br>+ }<br>+<br>+ /* Arms SMI for device 12 */<br>+ Store (One, TO12)<br>+ /* Put out a POST code */<br>+ Or (Arg0, 0xF0, P80)<br> }<br> <br> Method (\_WAK, 1, NotSerialized)<br> {<br> /* Re-enable fan, stop power led blinking */<br>- Store (One, FANP)<br>+ Store (One, FANM)<br> Store (One, PLED)<br> /* wake OK */<br> Return(Package(0x02){0x00, 0x00})<br>@@ -65,6 +103,22 @@<br> /* Root of the bus hierarchy */<br> Scope (\_SB)<br> {<br>+ Device (PWRB)<br>+ {<br>+ /* Power Button Device */<br>+ Name (_HID, EisaId ("PNP0C0C"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0B)<br>+ }<br>+ }<br>+ #include "southbridge/intel/i82371eb/acpi/intx.asl"<br>+<br>+ PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)<br>+ PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)<br>+ PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3)<br>+ PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4)<br>+<br> /* Top PCI device */<br> Device (PCI0)<br> {<br>@@ -106,10 +160,97 @@<br> Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },<br> <br> })<br>+ #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"<br> <br>-#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"<br>-#include "southbridge/intel/i82371eb/acpi/isabridge.asl"<br>+ /* Begin southbridge block */<br>+ Device (PX40)<br>+ {<br>+ Name(_ADR, 0x00040000)<br>+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)<br>+ Field (PIRQ, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PIRA, 8,<br>+ PIRB, 8,<br>+ PIRC, 8,<br>+ PIRD, 8<br>+ }<br>+<br>+ /* PNP Motherboard Resources */<br>+ Device (SYSR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0C02"))<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (BUF1, ResourceTemplate ()<br>+ {<br>+ /* PM register ports */<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)<br>+ /* SMBus register ports */<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)<br>+ /* PIIX4E ports */<br>+ /* Aliased DMA ports */<br>+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )<br>+ /* Aliased PIC ports */<br>+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )<br>+ /* Aliased timer ports */<br>+ IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, )<br>+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )<br>+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )<br>+ IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )<br>+ IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )<br>+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )<br>+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )<br>+ IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )<br>+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )<br>+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )<br>+ })<br>+ CreateWordField (BUF1, _Y06._MIN, PMLO)<br>+ CreateWordField (BUF1, _Y06._MAX, PMRL)<br>+ CreateWordField (BUF1, _Y07._MIN, SBLO)<br>+ CreateWordField (BUF1, _Y07._MAX, SBRL)<br>+<br>+ And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO)<br>+ And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO)<br>+ Store (PMLO, PMRL)<br>+ Store (SBLO, SBRL)<br>+ Return (BUF1)<br>+ }<br>+ }<br>+ #include "southbridge/intel/i82371eb/acpi/i82371eb.asl"<br>+ }<br>+ Device (PX43)<br>+ {<br>+ Name (_ADR, 0x00040003) // _ADR: Address<br>+ OperationRegion (IPMU, PCI_Config, PMBA, 0x02)<br>+ Field (IPMU, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PM00, 16<br>+ }<br>+<br>+ OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)<br>+ Field (ISMB, ByteAcc, NoLock, Preserve)<br>+ {<br>+ SB00, 16<br>+ }<br>+ }<br>+<br>+ #include "superio/winbond/w83977tf/acpi/superio.asl"<br> }<br>-#include "southbridge/intel/i82371eb/acpi/pirq.asl"<br>+ }<br>+<br>+ /* ACPI Message */<br>+ Scope (\_SI)<br>+ {<br>+ Method (_MSG, 1, NotSerialized)<br>+ {<br>+ If (LEqual (Arg0, Zero))<br>+ {<br>+ Store (One, MSG0)<br>+ }<br>+ Else<br>+ {<br>+ Store (Zero, MSG0)<br>+ }<br>+ }<br> }<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22473">change 22473</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e </div>
<div style="display:none"> Gerrit-Change-Number: 22473 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>