<p>Lin Huang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22467">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">rockchip/rk3399: mipi: correct phy parameter setting<br><br>As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0><br>should depend on frequency, so fix it.<br><br>Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1<br>Signed-off-by: Lin Huang <hl@rock-chips.com><br>---<br>M src/soc/rockchip/rk3399/include/soc/mipi.h<br>M src/soc/rockchip/rk3399/mipi.c<br>2 files changed, 75 insertions(+), 31 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22467/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h<br>index 2dfbc52..7dc6b14 100644<br>--- a/src/soc/rockchip/rk3399/include/soc/mipi.h<br>+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h<br>@@ -186,10 +186,22 @@<br> #define VCO_IN_CAP_CON_HIGH (0x2 << 1)<br> #define REF_BIAS_CUR_SEL BIT(0)<br> <br>-#define CP_CURRENT_3MA BIT(3)<br>+#define CP_CURRENT_1_5UA 0x1<br>+#define CP_CURRENT_4_5UA 0x2<br>+#define CP_CURRENT_7_5UA 0x6<br>+#define CP_CURRENT_6UA 0x9<br>+#define CP_CURRENT_12UA 0xb<br>+#define CP_CURRENT_SEL(val) ((val) & 0xf)<br>+<br> #define CP_PROGRAM_EN BIT(7)<br>+<br> #define LPF_PROGRAM_EN BIT(6)<br>-#define LPF_RESISTORS_20_KOHM 0<br>+#define LPF_RESISTORS_15_5KOHM 0x1<br>+#define LPF_RESISTORS_13KOHM 0x2<br>+#define LPF_RESISTORS_11_5KOHM 0x4<br>+#define LPF_RESISTORS_10_5KOHM 0x8<br>+#define LPF_RESISTORS_8KOHM 0x10<br>+#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)<br> <br> #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)<br> <br>@@ -271,9 +283,11 @@<br> MIPI_DCS_SET_DISPLAY_ON = 0x29,<br> };<br> <br>-struct dphy_pll_testdin_map {<br>+struct dphy_pll_parameter_map {<br> unsigned int max_mbps;<br>- u8 testdin;<br>+ u8 hsfreqrange;<br>+ u8 icpctrl;<br>+ u8 lpfctrl;<br> };<br> <br> struct rk_mipi_dsi {<br>diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c<br>index 9491b91..1f07491 100644<br>--- a/src/soc/rockchip/rk3399/mipi.c<br>+++ b/src/soc/rockchip/rk3399/mipi.c<br>@@ -47,26 +47,56 @@<br> mdelay(two_frames);<br> }<br> <br>-static const struct dphy_pll_testdin_map dptdin_map[] = {<br>- { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},<br>- { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},<br>- { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},<br>- { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},<br>- { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},<br>- { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},<br>- { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},<br>- {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},<br>- {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},<br>- {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}<br>+static const struct dphy_pll_parameter_map dppa_map[] = {<br>+ { 89, 0x00, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},<br>+ { 99, 0x10, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},<br>+ { 109, 0x20, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},<br>+ { 129, 0x01, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},<br>+ { 139, 0x11, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},<br>+ { 149, 0x21, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},<br>+ { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},<br>+ { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},<br>+ { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},<br>+ { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},<br>+ { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},<br>+ { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},<br>+ { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},<br>+ { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},<br>+ { 329, 0x05, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},<br>+ { 359, 0x15, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},<br>+ { 399, 0x25, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},<br>+ { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},<br>+ { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},<br>+ { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},<br>+ { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},<br>+ { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},<br>+ {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},<br>+ {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},<br>+ {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},<br>+ {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM}<br> };<br> <br>-static int max_mbps_to_testdin(unsigned int max_mbps)<br>+static int max_mbps_to_parameter(unsigned int max_mbps)<br> {<br> int i;<br> <br>- for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)<br>- if (dptdin_map[i].max_mbps > max_mbps)<br>- return dptdin_map[i].testdin;<br>+ for (i = 0; i < ARRAY_SIZE(dppa_map); i++) {<br>+ if (dppa_map[i].max_mbps >= max_mbps)<br>+ return i;<br>+ }<br> <br> return -1;<br> }<br>@@ -95,16 +125,16 @@<br> <br> static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)<br> {<br>- int testdin, vco;<br>-<br>+ int i, vco;<br> int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);<br>+<br> vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;<br> <br>- testdin = max_mbps_to_testdin(lane_mbps);<br>- if (testdin < 0) {<br>- printk(BIOS_DEBUG, "failed to get testdin for %dmbps\n",<br>- lane_mbps);<br>- return testdin;<br>+ i = max_mbps_to_parameter(lane_mbps);<br>+ if (i < 0) {<br>+ printk(BIOS_DEBUG,<br>+ "failed to get parameter for %dmbps clock\n", lane_mbps);<br>+ return i;<br> }<br> <br> /* Start by clearing PHY state */<br>@@ -119,14 +149,14 @@<br> REF_BIAS_CUR_SEL);<br> <br> rk_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,<br>- CP_CURRENT_3MA);<br>+ CP_CURRENT_SEL(dppa_map[i].icpctrl));<br> rk_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,<br> CP_PROGRAM_EN |<br> LPF_PROGRAM_EN |<br>- LPF_RESISTORS_20_KOHM);<br>-<br>+ LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));<br> rk_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,<br>- HSFREQRANGE_SEL(testdin));<br>+ HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));<br>+<br> rk_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,<br> INPUT_DIVIDER(dsi->input_div));<br> rk_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,<br>@@ -182,7 +212,7 @@<br> u32 i, pre;<br> u64 pclk, pllref, tmp, target_bps;<br> u32 m = 1, n = 1;<br>- u32 max_bps = 1500 * MHz;<br>+ u32 max_bps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps * MHz;<br> int bpp;<br> <br> bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);<br></pre><p>To view, visit <a href="https://review.coreboot.org/22467">change 22467</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22467"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1 </div>
<div style="display:none"> Gerrit-Change-Number: 22467 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lin Huang <hl@rock-chips.com> </div>