<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22452">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/x86/acpi: Add support for writing ACPI DBG2 table<br><br>Add a function to create an ACPI DBG2 table, which is a Microsoft<br>ACPI extension for providing a description of the available debug<br>interface on a board.<br><br>A convenience function is provided for creating a DBG2 table with<br>a 16550 UART based on a PCI device.<br><br>This is tested by generating a device and verifying it with iasl:<br><br>[000h 0000 4] Signature : "DBG2"<br>[004h 0004 4] Table Length : 00000061<br>[008h 0008 1] Revision : 00<br>[009h 0009 1] Checksum : 3B<br>[00Ah 0010 6] Oem ID : "CORE "<br>[010h 0016 8] Oem Table ID : "COREBOOT"<br>[018h 0024 4] Oem Revision : 00000000<br>[01Ch 0028 4] Asl Compiler ID : "CORE"<br>[020h 0032 4] Asl Compiler Revision : 00000000<br><br>[024h 0036 4] Info Offset : 0000002C<br>[028h 0040 4] Info Count : 00000001<br><br>[02Ch 0044 1] Revision : 00<br>[02Dh 0045 2] Length : 0035<br>[02Fh 0047 1] Register Count : 01<br>[030h 0048 2] Namepath Length : 000F<br>[032h 0050 2] Namepath Offset : 0026<br>[034h 0052 2] OEM Data Length : 0000<br>[036h 0054 2] OEM Data Offset : 0000<br>[038h 0056 2] Port Type : 8000<br>[03Ah 0058 2] Port Subtype : 0000<br>[03Ch 0060 2] Reserved : 0000<br>[03Eh 0062 2] Base Address Offset : 0016<br>[040h 0064 2] Address Size Offset : 0022<br><br>[042h 0066 12] Base Address Register : [Generic Address Structure]<br>[042h 0066 1] Space ID : 00 [SystemMemory]<br>[043h 0067 1] Bit Width : 00<br>[044h 0068 1] Bit Offset : 00<br>[045h 0069 1] Encoded Access Width : 03 [DWord Access:32]<br>[046h 0070 8] Address : 00000000FE034000<br><br>[04Eh 0078 4] Address Size : 00001000<br><br>[052h 0082 15] Namepath : "\_SB.PCI0.UAR2"<br><br>Raw Table Data: Length 97 (0x61)<br><br> 0000: 44 42 47 32 61 00 00 00 00 3B 43 4F 52 45 20 20 // DBG2a....;CORE<br> 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE<br> 0020: 00 00 00 00 2C 00 00 00 01 00 00 00 00 35 00 01 // ....,........5..<br> 0030: 0F 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00 // ..&.............<br> 0040: 22 00 00 00 00 03 00 40 03 FE 00 00 00 00 00 10 // "......@........<br> 0050: 00 00 5C 5F 53 42 2E 50 43 49 30 2E 55 41 52 32 // ..\_SB.PCI0.UAR2<br> 0060: 00 // .<br><br>Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/arch/x86/acpi.c<br>M src/arch/x86/include/arch/acpi.h<br>2 files changed, 149 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/22452/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c<br>index 02884c4..31a7ee4 100644<br>--- a/src/arch/x86/acpi.c<br>+++ b/src/arch/x86/acpi.c<br>@@ -658,6 +658,111 @@<br> return current;<br> }<br> <br>+void acpi_create_dbg2(acpi_dbg2_header_t *dbg2,<br>+ int port_type, int port_subtype,<br>+ acpi_addr_t *address, uint32_t address_size,<br>+ const char *device_path)<br>+{<br>+ uintptr_t current;<br>+ acpi_dbg2_device_t *device;<br>+ uint32_t *dbg2_addr_size;<br>+ acpi_header_t *header;<br>+ size_t path_len;<br>+ const char *path;<br>+ char *namespace;<br>+<br>+ /* Fill out header fields. */<br>+ current = (uintptr_t)dbg2;<br>+ memset(dbg2, 0, sizeof(acpi_dbg2_header_t));<br>+ header = &(dbg2->header);<br>+ header->revision = 0;<br>+ memcpy(header->signature, "DBG2", 4);<br>+ memcpy(header->oem_id, OEM_ID, 6);<br>+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);<br>+ memcpy(header->asl_compiler_id, ASLC, 4);<br>+<br>+ /* One debug device defined */<br>+ dbg2->devices_offset = sizeof(acpi_dbg2_header_t);<br>+ dbg2->devices_count = 1;<br>+ current += sizeof(acpi_dbg2_header_t);<br>+<br>+ /* Device comes after the header */<br>+ device = (acpi_dbg2_device_t *)current;<br>+ memset(device, 0, sizeof(acpi_dbg2_device_t));<br>+ current += sizeof(acpi_dbg2_device_t);<br>+<br>+ device->revision = 0;<br>+ device->address_count = 1;<br>+ device->port_type = port_type;<br>+ device->port_subtype = port_subtype;<br>+<br>+ /* Base Address comes after device structure */<br>+ memcpy((void *)current, address, sizeof(acpi_addr_t));<br>+ device->base_address_offset = current - (uintptr_t)device;<br>+ current += sizeof(acpi_addr_t);<br>+<br>+ /* Address Size comes after address structure */<br>+ dbg2_addr_size = (uint32_t *)current;<br>+ device->address_size_offset = current - (uintptr_t)device;<br>+ *dbg2_addr_size = address_size;<br>+ current += sizeof(uint32_t);<br>+<br>+ /* Namespace string comes last, use '.' if not provided */<br>+ path = device_path ? : ".";<br>+ /* Namespace string length includes NULL terminator */<br>+ path_len = strlen(path) + 1;<br>+ namespace = (char *)current;<br>+ device->namespace_string_length = path_len;<br>+ device->namespace_string_offset = current - (uintptr_t)device;<br>+ strncpy(namespace, path, path_len);<br>+ current += path_len;<br>+<br>+ /* Update structure lengths and checksum */<br>+ device->length = current - (uintptr_t)device;<br>+ header->length = current - (uintptr_t)dbg2;<br>+ header->checksum = acpi_checksum((uint8_t *)dbg2, header->length);<br>+}<br>+<br>+unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,<br>+ struct device *dev, uint8_t access_size)<br>+{<br>+ acpi_dbg2_header_t *dbg2 = (acpi_dbg2_header_t *)current;<br>+ struct resource *res;<br>+ acpi_addr_t address;<br>+<br>+ if (!dev)<br>+ return current;<br>+ res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>+ if (!res)<br>+ return current;<br>+<br>+ memset(&address, 0, sizeof(address));<br>+ if (res->flags & IORESOURCE_IO)<br>+ address.space_id = ACPI_ADDRESS_SPACE_IO;<br>+ else if (res->flags & IORESOURCE_MEM)<br>+ address.space_id = ACPI_ADDRESS_SPACE_MEMORY;<br>+ else<br>+ return current;<br>+<br>+ address.addrl = (uint32_t)res->base;<br>+ address.addrh = (uint32_t)((res->base >> 32) & 0xffffffff);<br>+ address.access_size = access_size;<br>+<br>+ acpi_create_dbg2(dbg2,<br>+ ACPI_DBG2_PORT_SERIAL,<br>+ ACPI_DBG2_PORT_SERIAL_16550,<br>+ &address, res->size,<br>+ acpi_device_path(dev));<br>+<br>+ if (dbg2->header.length) {<br>+ current += dbg2->header.length;<br>+ current = acpi_align_current(current);<br>+ acpi_add_table(rsdp, dbg2);<br>+ }<br>+<br>+ return current;<br>+}<br>+<br> void acpi_create_facs(acpi_facs_t *facs)<br> {<br> memset((void *)facs, 0, sizeof(acpi_facs_t));<br>diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h<br>index 1b23991..5418420 100644<br>--- a/src/arch/x86/include/arch/acpi.h<br>+++ b/src/arch/x86/include/arch/acpi.h<br>@@ -404,6 +404,43 @@<br> u16 flags; /* MPS INTI flags */<br> } __packed acpi_madt_irqoverride_t;<br> <br>+#define ACPI_DBG2_PORT_SERIAL 0x8000<br>+#define ACPI_DBG2_PORT_SERIAL_16550 0x0000<br>+#define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001<br>+#define ACPI_DBG2_PORT_SERIAL_ARM_PL011 0x0003<br>+#define ACPI_DBG2_PORT_SERIAL_ARM_SBSA 0x000e<br>+#define ACPI_DBG2_PORT_SERIAL_ARM_DDC 0x000f<br>+#define ACPI_DBG2_PORT_SERIAL_BCM2835 0x0010<br>+#define ACPI_DBG2_PORT_IEEE1394 0x8001<br>+#define ACPI_DBG2_PORT_IEEE1394_STANDARD 0x0000<br>+#define ACPI_DBG2_PORT_USB 0x8002<br>+#define ACPI_DBG2_PORT_USB_XHCI 0x0000<br>+#define ACPI_DBG2_PORT_USB_EHCI 0x0001<br>+#define ACPI_DBG2_PORT_NET 0x8003<br>+<br>+/* DBG2: Microsoft Debug Port Table 2 header */<br>+typedef struct acpi_dbg2_header {<br>+ struct acpi_table_header header;<br>+ uint32_t devices_offset;<br>+ uint32_t devices_count;<br>+} __attribute__ ((packed)) acpi_dbg2_header_t;<br>+<br>+/* DBG2: Microsoft Debug Port Table 2 device entry */<br>+typedef struct acpi_dbg2_device {<br>+ uint8_t revision;<br>+ uint16_t length;<br>+ uint8_t address_count;<br>+ uint16_t namespace_string_length;<br>+ uint16_t namespace_string_offset;<br>+ uint16_t oem_data_length;<br>+ uint16_t oem_data_offset;<br>+ uint16_t port_type;<br>+ uint16_t port_subtype;<br>+ uint8_t reserved[2];<br>+ uint16_t base_address_offset;<br>+ uint16_t address_size_offset;<br>+} __attribute__ ((packed)) acpi_dbg2_device_t;<br>+<br> /* FADT (Fixed ACPI Description Table) */<br> typedef struct acpi_fadt {<br> struct acpi_table_header header;<br>@@ -667,6 +704,13 @@<br> <br> void acpi_create_facs(acpi_facs_t *facs);<br> <br>+void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header,<br>+ int port_type, int port_subtype,<br>+ acpi_addr_t *address, uint32_t address_size,<br>+ const char *device_path);<br>+<br>+unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,<br>+ struct device *dev, uint8_t access_size);<br> void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,<br> unsigned long (*acpi_fill_dmar)(unsigned long));<br> unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags,<br></pre><p>To view, visit <a href="https://review.coreboot.org/22452">change 22452</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22452"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479 </div>
<div style="display:none"> Gerrit-Change-Number: 22452 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>