<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22411">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add more ACPI register definitions<br><br>Change-Id: I62a840499deed895cf474f1bfce1f399c970e589<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>1 file changed, 12 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/22411/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index cc85fdb..497169f 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -55,6 +55,18 @@<br> #define   PM_SERIRQ_ENABLE          BIT(7)<br> <br> #define PM_EVT_BLK                  0x60<br>+#define   WAK_STS                        BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */<br>+#define   PCIEXPWAK_STS                        BIT(14)<br>+#define   RTC_STS                     BIT(10)<br>+#define   PWRBTN_STS                  BIT(8)<br>+#define   GBL_STS                      BIT(5)<br>+#define   BM_STS                       BIT(4)<br>+#define   TIMER_STS                    BIT(0)<br>+#define   PCIEXPWAK_DIS                        BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */<br>+#define   RTC_EN                       BIT(10)<br>+#define   PWRBTN_EN                   BIT(8)<br>+#define   GBL_EN                       BIT(5)<br>+#define   TIMER_STS                    BIT(0)<br> #define PM1_CNT_BLK                    0x62<br> #define PM_TMR_BLK                       0x64<br> #define PM_CPU_CTRL                      0x66<br></pre><p>To view, visit <a href="https://review.coreboot.org/22411">change 22411</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22411"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I62a840499deed895cf474f1bfce1f399c970e589 </div>
<div style="display:none"> Gerrit-Change-Number: 22411 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>