<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22416">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp: Update cannonlake FSP header<br><br>Update cannonlake FSP header to revision 7.x.11.43.<br><br>TEST=None<br><br>Change-Id: I63c990e5766370a82dc1c044bcf744612229a605<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>3 files changed, 38 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/22416/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>index dded50d..876c9d2 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>@@ -917,10 +917,9 @@<br> **/<br> UINT8 CoreVoltageMode;<br> <br>-/** Offset 0x0207 - Minimum clr turbo ratio override<br>- Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83<br>+/** Offset 0x0207<br> **/<br>- UINT8 RingMinOcRatio;<br>+ UINT8 UnusedUpdSpace6;<br> <br> /** Offset 0x0208 - Maximum clr turbo ratio override<br> Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the<br>@@ -1075,7 +1074,7 @@<br> <br> /** Offset 0x0227<br> **/<br>- UINT8 UnusedUpdSpace6;<br>+ UINT8 UnusedUpdSpace7;<br> <br> /** Offset 0x0228 - PrmrrSize<br> 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000<br>@@ -1853,7 +1852,7 @@<br> <br> /** Offset 0x04C7<br> **/<br>- UINT8 UnusedUpdSpace7;<br>+ UINT8 UnusedUpdSpace8;<br> <br> /** Offset 0x04C8 - RAPL PL 2 Power<br> range[0;2^14-1]= [2047.875;0]in W, (224= Def)<br>@@ -2481,7 +2480,7 @@<br> <br> /** Offset 0x0579<br> **/<br>- UINT8 UnusedUpdSpace8;<br>+ UINT8 UnusedUpdSpace9;<br> <br> /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization<br> Range: 0-65535, default is 1000. @warning Do not change from the default<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>index 2a2412d..17b9f92 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>@@ -975,45 +975,51 @@<br> PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in<br> increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.<br> **/<br>- UINT16 McivrRfiFrequencyAdjust;<br>+ UINT8 McivrRfiFrequencyAdjust;<br> <br>-/** Offset 0x0310 - FIVR RFI Frequency<br>+/** Offset 0x030F - FIVR RFI Frequency<br> PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:<br> Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;<br> 0-1535 (Up to 153.5MHz) for 19MHz clock.<br> **/<br> UINT16 FivrRfiFrequency;<br> <br>-/** Offset 0x0312 - McIVR RFI Spread Spectrum<br>+/** Offset 0x0311 - McIVR RFI Spread Spectrum<br> PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-<br> 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.<br> **/<br> UINT8 McivrSpreadSpectrum;<br> <br>-/** Offset 0x0313 - FIVR RFI Spread Spectrum<br>+/** Offset 0x0312 - FIVR RFI Spread Spectrum<br> PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;<br> Range: 0.0% to 10.0% (0-100).<br> **/<br> UINT8 FivrSpreadSpectrum;<br> <br>-/** Offset 0x0314 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain<br>+/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain<br> Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation<br> feature enabled. <b>0: False</b>; 1: True<br> $EN_DIS<br> **/<br> UINT8 FastPkgCRampDisableFivr;<br> <br>-/** Offset 0x0315 - Slew Rate configuration for Deep Package C States for VR FIVR domain<br>+/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain<br> Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic<br> Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16<br> 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16<br> **/<br> UINT8 SlowSlewRateForFivr;<br> <br>-/** Offset 0x0316 - CpuBistData<br>+/** Offset 0x0315 - CpuBistData<br> Pointer CPU BIST Data<br> **/<br> UINT32 CpuBistData;<br>+<br>+/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.<br>+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox<br>+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.<br>+**/<br>+ UINT8 IslVrCmd;<br> <br> /** Offset 0x031A - ReservedCpuPostMemProduction<br> Reserved for CPU Post-Mem Production<br>@@ -2935,11 +2941,23 @@<br> **/<br> UINT8 CpuWakeUpTimer;<br> <br>-/** Offset 0x08A3 - ReservedCpuPostMemTest<br>+/** Offset 0x08A3 - Minimum Ring ratio limit override<br>+ Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo<br>+ ratio limit<br>+**/<br>+ UINT8 MinRingRatioLimit;<br>+<br>+/** Offset 0x08A4 - Minimum Ring ratio limit override<br>+ Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo<br>+ ratio limit<br>+**/<br>+ UINT8 MaxRingRatioLimit;<br>+<br>+/** Offset 0x08A5 - ReservedCpuPostMemTest<br> Reserved for CPU Post-Mem Test<br> $EN_DIS<br> **/<br>- UINT8 ReservedCpuPostMemTest[23];<br>+ UINT8 ReservedCpuPostMemTest[21];<br> <br> /** Offset 0x08BA - SgxSinitDataFromTpm<br> SgxSinitDataFromTpm default values<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>index 24f0883..665e5a0 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>@@ -142,9 +142,15 @@<br> #ifndef MRC_DDR_TYPE_LPDDR3<br> #define MRC_DDR_TYPE_LPDDR3 2<br> #endif<br>+#ifndef CPU_CFL//CNL<br>+#ifndef MRC_DDR_TYPE_LPDDR4<br>+#define MRC_DDR_TYPE_LPDDR4 3<br>+#endif<br>+#else//CFL<br> #ifndef MRC_DDR_TYPE_UNKNOWN<br> #define MRC_DDR_TYPE_UNKNOWN 3<br> #endif<br>+#endif//CPU_CFL-endif<br> <br> #define MAX_PROFILE_NUM 4 // number of memory profiles supported<br> #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported<br></pre><p>To view, visit <a href="https://review.coreboot.org/22416">change 22416</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I63c990e5766370a82dc1c044bcf744612229a605 </div>
<div style="display:none"> Gerrit-Change-Number: 22416 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>