<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22391">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51<br><br>Update FSP header files to match FSP v69_51.<br><br>Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>3 files changed, 114 insertions(+), 80 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/22391/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>index 354dd8a..b6d5c84 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>@@ -35,7 +35,7 @@<br> <br> #include <FspEas.h><br> <br>-#pragma pack(push, 1)<br>+#pragma pack(1)<br> <br> #define FSPT_UPD_SIGNATURE 0x545F4450554B4C47 /* 'GLKUPD_T' */<br> <br>@@ -43,6 +43,6 @@<br> <br> #define FSPS_UPD_SIGNATURE 0x535F4450554B4C47 /* 'GLKUPD_S' */<br> <br>-#pragma pack(pop)<br>+#pragma pack()<br> <br> #endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>index 6db6685..1f0072d 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>@@ -35,7 +35,7 @@<br> <br> #include <FspUpd.h><br> <br>-#pragma pack(push, 1)<br>+#pragma pack(1)<br> <br> <br> #define MAX_NODE_NUM 1<br>@@ -913,13 +913,7 @@<br> **/<br> UINT8 EnableSgx;<br> <br>-/** Offset 0x014B - PRMRR size<br>- PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>- 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>-**/<br>- UINT32 PrmrrSize;<br>-<br>-/** Offset 0x014F - Periodic Retraining Disable<br>+/** Offset 0x014B - Periodic Retraining Disable<br> Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic<br> Retraining for debug purposes. Periodic Retraining should be enabled in production.<br> Periodic retraining allows the platform to operate reliably over a larger voltage<br>@@ -929,6 +923,12 @@<br> 0x0:Enabled, 0x1:Disabled<br> **/<br> UINT8 PeriodicRetrainingDisable;<br>+<br>+/** Offset 0x014C - PRMRR size<br>+ PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>+ 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>+**/<br>+ UINT32 PrmrrSize;<br> <br> /** Offset 0x0150 - Enable Reset System<br> Enable FSP to trigger reset instead of returning reset request. 0x00: Return the<br>@@ -977,18 +977,18 @@<br> <br> /** Offset 0x016C<br> **/<br>- UINT8 ReservedFspmTestUpd[18];<br>+ UINT8 ReservedFspmTestUpd[20];<br> } FSP_M_TEST_CONFIG;<br> <br> /** Fsp M Restricted Configuration<br> **/<br> typedef struct {<br> <br>-/** Offset 0x017E<br>+/** Offset 0x0180<br> **/<br> UINT32 Signature;<br> <br>-/** Offset 0x0182<br>+/** Offset 0x0184<br> **/<br> UINT8 ReservedFspmRestrictedUpd[124];<br> } FSP_M_RESTRICTED_CONFIG;<br>@@ -1013,15 +1013,19 @@<br> **/<br> FSP_M_TEST_CONFIG FspmTestConfig;<br> <br>-/** Offset 0x017E<br>+/** Offset 0x0180<br> **/<br> FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;<br> <br>-/** Offset 0x01FE<br>+/** Offset 0x0200<br>+**/<br>+ UINT8 UnusedUpdSpace1[6];<br>+<br>+/** Offset 0x0206<br> **/<br> UINT16 UpdTerminator;<br> } FSPM_UPD;<br> <br>-#pragma pack(pop)<br>+#pragma pack()<br> <br> #endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>index 0992034..bbea05f 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>@@ -35,7 +35,7 @@<br> <br> #include <FspUpd.h><br> <br>-#pragma pack(push, 1)<br>+#pragma pack(1)<br> <br> <br> /** Fsp S Configuration<br>@@ -71,17 +71,16 @@<br> **/<br> UINT8 VmxEnable;<br> <br>-/** Offset 0x0025 - Memory region allocation for Processor Trace<br>- Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to<br>- 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)<br>+/** Offset 0x0025 - Depricated UPD<br>+ Depricated UPD<br> **/<br>- UINT8 ProcTraceMemSize;<br>+ UINT8 Reserved;<br> <br> /** Offset 0x0026 - Enable Processor Trace<br> Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.<br> $EN_DIS<br> **/<br>- UINT8 ProcTraceEnable;<br>+ UINT8 ProcessorTraceEnable;<br> <br> /** Offset 0x0027 - Eist<br> Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).<br>@@ -1476,56 +1475,56 @@<br> **/<br> UINT32 EmmcMasterSwCntl;<br> <br>-/** Offset 0x0318 - PCIe Selectable De-emphasis<br>+/** Offset 0x0318 - SGX Epoch 0<br>+ SGX Epoch 0. 0x0(Default).<br>+**/<br>+ UINT64 SgxEpoch0;<br>+<br>+/** Offset 0x0320 - SGX Epoch 1<br>+ SGX Epoch 1. 0x0(Default).<br>+**/<br>+ UINT64 SgxEpoch1;<br>+<br>+/** Offset 0x0328 - MicrocodePatchAddress<br>+ MicrocodePatchAddress. 0x0(Default).<br>+**/<br>+ UINT64 MicrocodePatchAddress;<br>+<br>+/** Offset 0x0330 - PCIe Selectable De-emphasis<br> When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis<br> for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).<br> **/<br> UINT8 PcieRpSelectableDeemphasis[6];<br> <br>-/** Offset 0x031E - Monitor Mwait Enable<br>+/** Offset 0x0336 - Monitor Mwait Enable<br> Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux<br> based OS, this should be Disabled. 0:Disable, 1:Enable(Default).<br> $EN_DIS<br> **/<br> UINT8 MonitorMwaitEnable;<br> <br>-/** Offset 0x031F - Universal Audio Architecture compliance for DSP enabled system<br>+/** Offset 0x0337 - Universal Audio Architecture compliance for DSP enabled system<br> 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox<br> driver or SST driver supported).<br> $EN_DIS<br> **/<br> UINT8 HdAudioDspUaaCompliance;<br> <br>-/** Offset 0x0320 - IRQ Interrupt Polarity Control<br>+/** Offset 0x0338 - IRQ Interrupt Polarity Control<br> Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low<br> **/<br> UINT32 IPC[4];<br> <br>-/** Offset 0x0330 - Disable ModPHY dynamic power gate<br>+/** Offset 0x0348 - Disable ModPHY dynamic power gate<br> Disable ModPHY dynamic power gate for the specific SATA port.<br> **/<br> UINT8 SataPortsDisableDynamicPg[2];<br> <br>-/** Offset 0x0332 - Init CPU during S3 resume<br>+/** Offset 0x034A - Init CPU during S3 resume<br> 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume.<br> $EN_DIS<br> **/<br> UINT8 InitS3Cpu;<br>-<br>-/** Offset 0x0333 - SGX Epoch 0<br>- SGX Epoch 0. 0x0(Default).<br>-**/<br>- UINT64 SgxEpoch0;<br>-<br>-/** Offset 0x033B - SGX Epoch 1<br>- SGX Epoch 1. 0x0(Default).<br>-**/<br>- UINT64 SgxEpoch1;<br>-<br>-/** Offset 0x0343 - MicrocodePatchAddress<br>- MicrocodePatchAddress. 0x0(Default).<br>-**/<br>- UINT64 MicrocodePatchAddress;<br> <br> /** Offset 0x034B - CNVi Mode<br> Selects CNVi Mode. 0:Disable, 1:Auto(Default).<br>@@ -1562,47 +1561,47 @@<br> **/<br> UINT8 HgDgpuPwrEnable[8];<br> <br>-/** Offset 0x035F - dGPU Delay after power enable<br>+/** Offset 0x035F - HG Enable<br>+ Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable<br>+ 0x1:Enabled, 0x0:Disabled<br>+**/<br>+ UINT8 HgEnabled;<br>+<br>+/** Offset 0x0360 - dGPU Delay after power enable<br> Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,<br> 300 : Default<br> 0 : Minimum , 1000 : Maximum , 300 : Default<br> **/<br> UINT16 HgDelayAfterPwrEn;<br> <br>-/** Offset 0x0361 - dGPU Delay after hold reset<br>+/** Offset 0x0362 - dGPU Delay after hold reset<br> Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,<br> 100 : Default<br> 0 : Minimum , 1000 : Maximum , 100 : Default<br> **/<br> UINT16 HgDelayAfterHoldReset;<br> <br>-/** Offset 0x0363 - HG Enable<br>- Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable<br>- 0x1:Enabled, 0x0:Disabled<br>+/** Offset 0x0364 - CpuS3ResumeMtrrDataSize<br>+ Size of S3 resume MTRR data.<br> **/<br>- UINT8 HgEnabled;<br>+ UINT16 CpuS3ResumeMtrrDataSize;<br> <br>-/** Offset 0x0364 - PAVP ASMF<br>+/** Offset 0x0366 - PAVP ASMF<br> Enable/Disable PAVP ASMF 0:Disable, 1:Enable(Default).<br> $EN_DIS<br> **/<br> UINT8 PavpAsmf;<br> <br>-/** Offset 0x0365 - CpuS3ResumeMtrrDataSize<br>- Size of S3 resume MTRR data.<br>-**/<br>- UINT16 CpuS3ResumeMtrrDataSize;<br>-<br>-/** Offset 0x0367 - CpuS3ResumeMtrrData<br>- Pointer CPU S3 Resume MTRR Data<br>-**/<br>- UINT32 CpuS3ResumeMtrrData;<br>-<br>-/** Offset 0x036B - PAVP Auto TearDown Grace Period Enable<br>+/** Offset 0x0367 - PAVP Auto TearDown Grace Period Enable<br> Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default).<br> $EN_DIS<br> **/<br> UINT8 AutoTearDownGracePeriod;<br>+<br>+/** Offset 0x0368 - CpuS3ResumeMtrrData<br>+ Pointer CPU S3 Resume MTRR Data<br>+**/<br>+ UINT32 CpuS3ResumeMtrrData;<br> <br> /** Offset 0x036C - SeC EndOfPost EnableDisable<br> Enable/Disable SeC EOPEnable 0:Disable, 1:Enable(Default).<br>@@ -1628,26 +1627,53 @@<br> **/<br> UINT8 OsBoot;<br> <br>-/** Offset 0x0370 - AP threads Idle Manner<br>+/** Offset 0x0370 - System Vendor ID<br>+ Upd for vendor ID for assigning to devices <br>+**/<br>+ UINT16 SiSVID;<br>+<br>+/** Offset 0x0372 - Sub system Vendor ID<br>+ Upd for subsystem ID for assigning to devices<br>+**/<br>+ UINT16 SiSSID;<br>+<br>+/** Offset 0x0374 - CpuBistData<br>+ Pointer CPU BIST Data<br>+**/<br>+ UINT32 CpuBistData;<br>+<br>+/** Offset 0x0378 - Base of memory region allocated for Processor Trace<br>+ Base address of memory region allocated for Processor Trace. Processor Trace requires<br>+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b><br>+**/<br>+ UINT64 ProcessorTraceMemBase;<br>+<br>+/** Offset 0x0380 - Memory region allocation for Processor Trace<br>+ Length in bytes of memory region allocated for Processor Trace. Processor Trace<br>+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b><br>+**/<br>+ UINT32 ProcessorTraceMemLength;<br>+<br>+/** Offset 0x0384 - AP threads Idle Manner<br> AP threads Idle Manner for waiting signal to run 1:HALT loop 2:MWAIT loop 3:RUN lOOP<br> $EN_DIS<br> **/<br> UINT8 ApIdleManner;<br> <br>-/** Offset 0x0371<br>+/** Offset 0x0385<br> **/<br>- UINT8 ReservedFspsUpd[3];<br>+ UINT8 ReservedFspsUpd[11];<br> } FSP_S_CONFIG;<br> <br> /** Fsp S Test Configuration<br> **/<br> typedef struct {<br> <br>-/** Offset 0x0374<br>+/** Offset 0x0390<br> **/<br> UINT32 Signature;<br> <br>-/** Offset 0x0378<br>+/** Offset 0x0394<br> **/<br> UINT8 ReservedFspsTestUpd[12];<br> } FSP_S_TEST_CONFIG;<br>@@ -1656,50 +1682,50 @@<br> **/<br> typedef struct {<br> <br>-/** Offset 0x0384<br>+/** Offset 0x03A0<br> **/<br> UINT32 Signature;<br> <br>-/** Offset 0x0388 - Selective enable SGX<br>+/** Offset 0x03A4 - Selective enable SGX<br> Selective enable SGX. 0xFFFF(Default).<br> **/<br> UINT16 SelectiveEnableSgx;<br> <br>-/** Offset 0x038A - SGX debug mode<br>+/** Offset 0x03A6 - SGX debug mode<br> Select SGX mode. 0:Disable(default), 1:Enable<br> 0:Disable(default), 1:Enable<br> **/<br> UINT8 SgxDebugMode;<br> <br>-/** Offset 0x038B - SGX Launch Control Policy Mode<br>+/** Offset 0x03A7 - SGX Launch Control Policy Mode<br> Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)<br> 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode<br> **/<br> UINT8 SgxLcp;<br> <br>-/** Offset 0x038C - LE KeyHash0<br>+/** Offset 0x03A8 - LE KeyHash0<br> LE KeyHash0. 0x0(Default).<br> **/<br> UINT64 SgxLePubKeyHash0;<br> <br>-/** Offset 0x0394 - LE KeyHash1<br>+/** Offset 0x03B0 - LE KeyHash1<br> LE KeyHash1. 0x0(Default).<br> **/<br> UINT64 SgxLePubKeyHash1;<br> <br>-/** Offset 0x039C - LE KeyHash2<br>+/** Offset 0x03B8 - LE KeyHash2<br> LE KeyHash2. 0x0(Default).<br> **/<br> UINT64 SgxLePubKeyHash2;<br> <br>-/** Offset 0x03A4 - LE KeyHash3<br>+/** Offset 0x03C0 - LE KeyHash3<br> LE KeyHash3. 0x0(Default).<br> **/<br> UINT64 SgxLePubKeyHash3;<br> <br>-/** Offset 0x03AC<br>+/** Offset 0x03C8<br> **/<br>- UINT8 ReservedFspsRestrictedUpd[2];<br>+ UINT8 ReservedFspsRestrictedUpd[8];<br> } FSP_S_RESTRICTED_CONFIG;<br> <br> /** Fsp S UPD Configuration<br>@@ -1714,19 +1740,23 @@<br> **/<br> FSP_S_CONFIG FspsConfig;<br> <br>-/** Offset 0x0374<br>+/** Offset 0x0390<br> **/<br> FSP_S_TEST_CONFIG FspsTestConfig;<br> <br>-/** Offset 0x0384<br>+/** Offset 0x03A0<br> **/<br> FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;<br> <br>-/** Offset 0x03AE<br>+/** Offset 0x03D0<br>+**/<br>+ UINT8 UnusedUpdSpace7[6];<br>+<br>+/** Offset 0x03D6<br> **/<br> UINT16 UpdTerminator;<br> } FSPS_UPD;<br> <br>-#pragma pack(pop)<br>+#pragma pack()<br> <br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22391">change 22391</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5 </div>
<div style="display:none"> Gerrit-Change-Number: 22391 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>