<p>Vaibhav Shankar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22389">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Fix xhci ASL<br><br>During S3 cycling, system entered S3 only once and falied to<br>enter S3 the second time. The system gets stuck at this point<br>and we have to do a cold reboot to restore the system.<br><br>This patch removes SS clk trunk gating. This helps in continuous<br>cycling of S3.<br><br>TEST=run powerd_dbus_suspend multiple times and check if<br>the system enters and resumes from S3.<br><br>Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e<br>Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com><br>---<br>M src/soc/intel/cannonlake/acpi/xhci.asl<br>1 file changed, 2 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/22389/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl<br>index 4c1b08b..f3b300b 100644<br>--- a/src/soc/intel/cannonlake/acpi/xhci.asl<br>+++ b/src/soc/intel/cannonlake/acpi/xhci.asl<br>@@ -94,9 +94,6 @@<br>          Offset (0x10),<br>                , 16,<br>                 XMEM, 16,       /* MEM_BASE */<br>-               Offset (0x50),  /* XHCLKGTEN */<br>-              , 2,<br>-         STGE, 1,        /* SS Link Trunk clock gating enable */<br>               Offset (0x74),<br>                D0D3, 2,        /* POWERSTATE */<br>              , 6,<br>@@ -131,9 +128,8 @@<br>                     Return<br>                }<br> <br>-         /* Disable d3hot and SS link trunk clock gating */<br>+           /* Disable d3hot */<br>           Store(Zero, ^D3HE)<br>-           Store(Zero, ^STGE)<br> <br>                 /* If device is in D3, set back to D0 */<br>              If (LEqual (^D0D3, 3)) {<br>@@ -171,9 +167,8 @@<br>                 /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */<br>                Store (3, ^UPSW)<br> <br>-          /* Enable d3hot and SS link trunk clock gating */<br>+            /* Enable d3hot */<br>                 Store(One, ^D3HE)<br>-                Store(One, ^STGE)<br> <br>                 /* Now put device in D3 */<br>            Store (3, Local0)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22389">change 22389</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22389"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e </div>
<div style="display:none"> Gerrit-Change-Number: 22389 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar@intel.com> </div>