<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22360">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Add Intel common SPI support<br><br>SOC need to select specific macros need to compile<br>common SPI code.<br><br>Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A src/soc/intel/common/block/spi/Kconfig<br>A src/soc/intel/common/block/spi/Makefile.inc<br>A src/soc/intel/common/block/spi/spi.c<br>3 files changed, 98 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/22360/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/spi/Kconfig b/src/soc/intel/common/block/spi/Kconfig<br>new file mode 100644<br>index 0000000..bebb87a<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/spi/Kconfig<br>@@ -0,0 +1,5 @@<br>+config SOC_INTEL_COMMON_BLOCK_SPI<br>+ bool<br>+ help<br>+ Intel Processor common SPI support<br>+<br>diff --git a/src/soc/intel/common/block/spi/Makefile.inc b/src/soc/intel/common/block/spi/Makefile.inc<br>new file mode 100644<br>index 0000000..9c71d64<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/spi/Makefile.inc<br>@@ -0,0 +1,14 @@<br>+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c<br>+<br>+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c<br>+<br>+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c<br>+<br>+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c<br>+<br>+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c<br>+<br>+ifeq ($(CONFIG_SPI_FLASH_SMM),y)<br>+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += spi.c<br>+endif<br>+<br>diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c<br>new file mode 100644<br>index 0000000..7671ab9<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/spi/spi.c<br>@@ -0,0 +1,79 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_def.h><br>+#include <device/pci_ids.h><br>+#include <device/spi.h><br>+#include <intelblocks/fast_spi.h><br>+#include <intelblocks/gspi.h><br>+#include <soc/pci_devs.h><br>+#include <spi-generic.h><br>+<br>+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {<br>+ { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },<br>+#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI)<br>+ { .ctrlr = &gspi_ctrlr, .bus_start = 1,<br>+ .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},<br>+#endif<br>+};<br>+<br>+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);<br>+<br>+#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)<br>+<br>+static int spi_dev_to_bus(struct device *dev)<br>+{<br>+ return spi_devfn_to_bus(dev->path.pci.devfn);<br>+}<br>+<br>+static struct spi_bus_operations spi_bus_ops = {<br>+ .dev_to_bus = &spi_dev_to_bus,<br>+};<br>+<br>+static struct device_operations spi_dev_ops = {<br>+ .read_resources = &pci_dev_read_resources,<br>+ .set_resources = &pci_dev_set_resources,<br>+ .enable_resources = &pci_dev_enable_resources,<br>+ .scan_bus = &scan_generic_bus,<br>+ .ops_spi_bus = &spi_bus_ops,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+ PCI_DEVICE_ID_INTEL_SPT_SPI1,<br>+ PCI_DEVICE_ID_INTEL_SPT_SPI2,<br>+ PCI_DEVICE_ID_INTEL_SPT_SPI3,<br>+ PCI_DEVICE_ID_INTEL_APL_SPI0,<br>+ PCI_DEVICE_ID_INTEL_APL_SPI1,<br>+ PCI_DEVICE_ID_INTEL_APL_SPI2,<br>+ PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI,<br>+ PCI_DEVICE_ID_INTEL_GLK_SPI0,<br>+ PCI_DEVICE_ID_INTEL_GLK_SPI1,<br>+ PCI_DEVICE_ID_INTEL_GLK_SPI2,<br>+ PCI_DEVICE_ID_INTEL_CNL_SPI0,<br>+ PCI_DEVICE_ID_INTEL_CNL_SPI1,<br>+ PCI_DEVICE_ID_INTEL_CNL_SPI2,<br>+ PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,<br>+ 0<br>+};<br>+<br>+static const struct pci_driver pch_spi __pci_driver = {<br>+ .ops = &spi_dev_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22360">change 22360</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c </div>
<div style="display:none"> Gerrit-Change-Number: 22360 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>