<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22327">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Refactor setting default dll settings<br><br>This patch pushes these large default delay tables to a different file<br>to reduce cluttering up the actual raminit source. While doing so it<br>also uses more but smaller arrays and also adds the respective default<br>delays for DDR3 which are not yet used in this patch.<br><br>This patch add a function to set the read DQS delays instead of just<br>programming magic values. (This will prove useful for DQS read<br>training)<br><br>To prepare for adding trainings on the delay values it stores these<br>default delays in the sysinfo struct to program those. Later when<br>trainings are implemented those trained values will be used instead of<br>these safe default values, via using the cached sysinfo in 'mrc' cache.<br><br>Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/Makefile.inc<br>M src/northbridge/intel/x4x/raminit_ddr2.c<br>A src/northbridge/intel/x4x/raminit_tables.c<br>M src/northbridge/intel/x4x/x4x.h<br>4 files changed, 403 insertions(+), 106 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/22327/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc<br>index d910f92..0e5a4a3 100644<br>--- a/src/northbridge/intel/x4x/Makefile.inc<br>+++ b/src/northbridge/intel/x4x/Makefile.inc<br>@@ -21,6 +21,7 @@<br> romstage-y += raminit_ddr2.c<br> romstage-y += ram_calc.c<br> romstage-y += rcven.c<br>+romstage-y += raminit_tables.c<br> <br> ramstage-y += acpi.c<br> ramstage-y += ram_calc.c<br>diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c<br>index 4958226..c427f63 100644<br>--- a/src/northbridge/intel/x4x/raminit_ddr2.c<br>+++ b/src/northbridge/intel/x4x/raminit_ddr2.c<br>@@ -26,6 +26,7 @@<br> #else<br> #include <southbridge/intel/i82801jx/i82801jx.h><br> #endif<br>+#include <string.h><br> #include "iomap.h"<br> #include "x4x.h"<br> <br>@@ -344,6 +345,24 @@<br> }<br> }<br> <br>+static void rt_set_dqs(u8 channel, u8 lane, u8 rank,<br>+ struct rt_dqs_setting *dqs_setting)<br>+{<br>+ u8 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4);<br>+ u8 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4);<br>+ printk(RAM_SPEW, "RT DQS: ch%d, L%d, %d.%d\n", channel, lane,<br>+ dqs_setting->tap,<br>+ dqs_setting->pi);<br>+<br>+ saved_tap &= ~(0xf << (rank * 4));<br>+ saved_tap |= dqs_setting->tap << (rank * 4);<br>+ MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap;<br>+<br>+ saved_pi &= ~(0x7 << (rank * 3));<br>+ saved_pi |= dqs_setting->pi << (rank * 3);<br>+ MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi;<br>+}<br>+<br> static void timings_ddr2(struct sysinfo *s)<br> {<br> u8 i;<br>@@ -574,7 +593,6 @@<br> u8 i, j, r, reg8, clk, async = 0;<br> u16 reg16 = 0;<br> u32 reg32 = 0;<br>- u8 lane;<br> <br> MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04;<br> MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8;<br>@@ -660,60 +678,6 @@<br> MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40;<br> MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400;<br> <br>- static const struct dll_setting dll_setting_667[23] = {<br>- // tap pi db delay<br>- {13, 0, 1, 0, 0},<br>- {4, 1, 0, 0, 0},<br>- {13, 0, 1, 0, 0},<br>- {4, 5, 0, 0, 0},<br>- {4, 1, 0, 0, 0},<br>- {4, 1, 0, 0, 0},<br>- {4, 1, 0, 0, 0},<br>- {1, 5, 1, 1, 1},<br>- {1, 6, 1, 1, 1},<br>- {2, 0, 1, 1, 1},<br>- {2, 1, 1, 1, 1},<br>- {2, 1, 1, 1, 1},<br>- {14, 6, 1, 0, 0},<br>- {14, 3, 1, 0, 0},<br>- {14, 0, 1, 0, 0},<br>- {9, 0, 0, 0, 1},<br>- {9, 1, 0, 0, 1},<br>- {9, 2, 0, 0, 1},<br>- {9, 2, 0, 0, 1},<br>- {9, 1, 0, 0, 1},<br>- {6, 4, 0, 0, 1},<br>- {6, 2, 0, 0, 1},<br>- {5, 4, 0, 0, 1}<br>- };<br>-<br>- static const struct dll_setting dll_setting_800[23] = {<br>- // tap pi db delay<br>- {11, 5, 1, 0, 0},<br>- {0, 5, 1, 1, 0},<br>- {11, 5, 1, 0, 0},<br>- {1, 4, 1, 1, 0},<br>- {0, 5, 1, 1, 0},<br>- {0, 5, 1, 1, 0},<br>- {0, 5, 1, 1, 0},<br>- {2, 5, 1, 1, 1},<br>- {2, 6, 1, 1, 1},<br>- {3, 0, 1, 1, 1},<br>- {3, 0, 1, 1, 1},<br>- {3, 3, 1, 1, 1},<br>- {2, 0, 1, 1, 1},<br>- {1, 3, 1, 1, 1},<br>- {0, 3, 1, 1, 1},<br>- {9, 3, 0, 0, 1},<br>- {9, 4, 0, 0, 1},<br>- {9, 5, 0, 0, 1},<br>- {9, 6, 0, 0, 1},<br>- {10, 0, 0, 0, 1},<br>- {8, 1, 0, 0, 1},<br>- {7, 5, 0, 0, 1},<br>- {6, 2, 0, 0, 1}<br>- };<br>-<br> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {<br> MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc;<br> MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc;<br>@@ -723,21 +687,21 @@<br> <br> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {<br> if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) {<br>- clkset0(i, &dll_setting_667[CLKSET0]);<br>- clkset1(i, &dll_setting_667[CLKSET1]);<br>- ctrlset0(i, &dll_setting_667[CTRL0]);<br>- ctrlset1(i, &dll_setting_667[CTRL1]);<br>- ctrlset2(i, &dll_setting_667[CTRL2]);<br>- ctrlset3(i, &dll_setting_667[CTRL3]);<br>- cmdset(i, &dll_setting_667[CMD]);<br>+ clkset0(i, &default_ddr2_667_ctrl[CLKSET0]);<br>+ clkset1(i, &default_ddr2_667_ctrl[CLKSET1]);<br>+ ctrlset0(i, &default_ddr2_667_ctrl[CTRL0]);<br>+ ctrlset1(i, &default_ddr2_667_ctrl[CTRL1]);<br>+ ctrlset2(i, &default_ddr2_667_ctrl[CTRL2]);<br>+ ctrlset3(i, &default_ddr2_667_ctrl[CTRL3]);<br>+ cmdset(i, &default_ddr2_667_ctrl[CMD]);<br> } else {<br>- clkset0(i, &dll_setting_800[CLKSET0]);<br>- clkset1(i, &dll_setting_800[CLKSET1]);<br>- ctrlset0(i, &dll_setting_800[CTRL0]);<br>- ctrlset1(i, &dll_setting_800[CTRL1]);<br>- ctrlset2(i, &dll_setting_800[CTRL2]);<br>- ctrlset3(i, &dll_setting_800[CTRL3]);<br>- cmdset(i, &dll_setting_800[CMD]);<br>+ clkset0(i, &default_ddr2_800_ctrl[CLKSET0]);<br>+ clkset1(i, &default_ddr2_800_ctrl[CLKSET1]);<br>+ ctrlset0(i, &default_ddr2_800_ctrl[CTRL0]);<br>+ ctrlset1(i, &default_ddr2_800_ctrl[CTRL1]);<br>+ ctrlset2(i, &default_ddr2_800_ctrl[CTRL2]);<br>+ ctrlset3(i, &default_ddr2_800_ctrl[CTRL3]);<br>+ cmdset(i, &default_ddr2_800_ctrl[CMD]);<br> }<br> }<br> <br>@@ -837,32 +801,82 @@<br> <br> if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz)<br> MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1;<br>+}<br> <br>- // Program DQ/DQS dll settings<br>- reg32 = 0;<br>- FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {<br>+static void select_default_dq_dqs_settings(struct sysinfo *s)<br>+{<br>+ int ch, lane, rank;<br>+<br>+ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {<br> for (lane = 0; lane < 8; lane++) {<br>- if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)<br>- reg32 = 0x06db7777;<br>- else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz)<br>- reg32 = 0x00007777;<br>- MCHBAR32(0x400*i + 0x540 + lane*4) =<br>- (MCHBAR32(0x400*i + 0x540 + lane*4) & 0x0fffffff) |<br>- reg32;<br>+ FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) {<br>+ switch (s->selected_timings.mem_clk) {<br>+ case MEM_CLOCK_667MHz:<br>+ s->rt_dqs[ch][rank][lane].tap = 7;<br>+ s->rt_dqs[ch][rank][lane].pi = 2;<br>+ break;<br>+ case MEM_CLOCK_800MHz:<br>+ if (s->spd_type == DDR2) {<br>+ s->rt_dqs[ch][rank][lane].tap = 7;<br>+ s->rt_dqs[ch][rank][lane].pi = 0;<br>+ } else { /* DDR3 */<br>+ s->rt_dqs[ch][rank][lane].tap = 6;<br>+ s->rt_dqs[ch][rank][lane].pi = 2;<br>+ }<br>+ break;<br>+ case MEM_CLOCK_1066MHz:<br>+ s->rt_dqs[ch][rank][lane].tap = 5;<br>+ s->rt_dqs[ch][rank][lane].pi = 2;<br>+ break;<br>+ case MEM_CLOCK_1333MHz:<br>+ s->rt_dqs[ch][rank][lane].tap = 7;<br>+ s->rt_dqs[ch][rank][lane].pi = 0;<br>+ break;<br>+ default: /* not supported */<br>+ break;<br>+ }<br>+ }<br>+ switch (s->selected_timings.mem_clk) {<br>+ case MEM_CLOCK_667MHz:<br>+ memcpy(s->dqs_settings[ch],<br>+ default_ddr2_667_dqs,<br>+ sizeof(s->dqs_settings[ch]));<br>+ memcpy(s->dq_settings[ch],<br>+ default_ddr2_667_dq,<br>+ sizeof(s->dq_settings[ch]));<br>+<br>+ break;<br>+ case MEM_CLOCK_800MHz:<br>+ if (s->spd_type == DDR2) {<br>+ memcpy(s->dqs_settings[ch],<br>+ default_ddr2_800_dqs,<br>+ sizeof(s->dqs_settings[ch]));<br>+ memcpy(s->dq_settings[ch],<br>+ default_ddr2_800_dq,<br>+ sizeof(s->dq_settings[ch]));<br>+ }<br>+ /* else TODO */<br>+ break;<br>+ default: /* TODO */<br>+ break;<br>+ }<br> }<br> }<br>+}<br> <br>- FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {<br>- if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) {<br>- for (lane = 0; lane < 8; lane++)<br>- dqsset(i, lane, &dll_setting_667[DQS1+lane]);<br>- for (lane = 0; lane < 8; lane++)<br>- dqset(i, lane, &dll_setting_667[DQ1+lane]);<br>- } else {<br>- for (lane = 0; lane < 8; lane++)<br>- dqsset(i, lane, &dll_setting_800[DQS1+lane]);<br>- for (lane = 0; lane < 8; lane++)<br>- dqset(i, lane, &dll_setting_800[DQ1+lane]);<br>+static void set_all_dq_dqs_dll_settings(struct sysinfo *s)<br>+{<br>+ // Program DQ/DQS dll settings<br>+ int ch, lane, rank;<br>+<br>+ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {<br>+ for (lane = 0; lane < 8; lane++) {<br>+ FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) {<br>+ rt_set_dqs(ch, lane, rank,<br>+ &s->rt_dqs[ch][rank][lane]);<br>+ }<br>+ dqsset(ch, lane, &s->dqs_settings[ch][lane]);<br>+ dqset(ch, lane, &s->dq_settings[ch][lane]);<br> }<br> }<br> }<br>@@ -1492,6 +1506,9 @@<br> <br> // Program DLL<br> dll_ddr2(s);<br>+ if (!fast_boot)<br>+ select_default_dq_dqs_settings(s);<br>+ set_all_dq_dqs_dll_settings(s);<br> <br> // RCOMP<br> if (s->boot_path != BOOT_PATH_WARM_RESET) {<br>diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c<br>new file mode 100644<br>index 0000000..3cbba13<br>--- /dev/null<br>+++ b/src/northbridge/intel/x4x/raminit_tables.c<br>@@ -0,0 +1,271 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; either version 2 of<br>+ * the License, or (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <stdint.h><br>+#include "x4x.h"<br>+<br>+const struct dll_setting default_ddr2_667_ctrl[7] = {<br>+ /* tap pi db delay coarse*/<br>+ {13, 0, 1, 0, 0, 0}, /* clkset0 */<br>+ {4, 1, 0, 0, 0, 0}, /* ctrl0 */<br>+ {13, 0, 1, 0, 0, 0}, /* clkset1 */<br>+ {4, 5, 0, 0, 0, 0}, /* cmd */<br>+ {4, 1, 0, 0, 0, 0}, /* ctrl1 */<br>+ {4, 1, 0, 0, 0, 0}, /* ctrl2 */<br>+ {4, 1, 0, 0, 0, 0}, /* ctrl3 */<br>+};<br>+<br>+const struct dll_setting default_ddr2_667_dqs[8] = {<br>+ {1, 5, 1, 1, 1, 0},<br>+ {1, 6, 1, 1, 1, 0},<br>+ {2, 0, 1, 1, 1, 0},<br>+ {2, 1, 1, 1, 1, 0},<br>+ {2, 1, 1, 1, 1, 0},<br>+ {14, 6, 1, 0, 0, 0},<br>+ {14, 3, 1, 0, 0, 0},<br>+ {14, 0, 1, 0, 0, 0},<br>+};<br>+<br>+const struct dll_setting default_ddr2_667_dq[8] = {<br>+ {9, 0, 0, 0, 1, 0},<br>+ {9, 1, 0, 0, 1, 0},<br>+ {9, 2, 0, 0, 1, 0},<br>+ {9, 2, 0, 0, 1, 0},<br>+ {9, 1, 0, 0, 1, 0},<br>+ {6, 4, 0, 0, 1, 0},<br>+ {6, 2, 0, 0, 1, 0},<br>+ {5, 4, 0, 0, 1, 0}<br>+};<br>+<br>+const struct dll_setting default_ddr2_800_ctrl[7] = {<br>+ /* tap pi db delay coarse */<br>+ {11, 5, 1, 0, 0, 0},<br>+ {0, 5, 1, 1, 0, 0},<br>+ {11, 5, 1, 0, 0, 0},<br>+ {1, 4, 1, 1, 0, 0},<br>+ {0, 5, 1, 1, 0, 0},<br>+ {0, 5, 1, 1, 0, 0},<br>+ {0, 5, 1, 1, 0, 0},<br>+};<br>+<br>+const struct dll_setting default_ddr2_800_dqs[8] = {<br>+ {2, 5, 1, 1, 1, 0},<br>+ {2, 6, 1, 1, 1, 0},<br>+ {3, 0, 1, 1, 1, 0},<br>+ {3, 0, 1, 1, 1, 0},<br>+ {3, 3, 1, 1, 1, 0},<br>+ {2, 0, 1, 1, 1, 0},<br>+ {1, 3, 1, 1, 1, 0},<br>+ {0, 3, 1, 1, 1, 0},<br>+};<br>+<br>+const struct dll_setting default_ddr2_800_dq[8] = {<br>+ {9, 3, 0, 0, 1, 0},<br>+ {9, 4, 0, 0, 1, 0},<br>+ {9, 5, 0, 0, 1, 0},<br>+ {9, 6, 0, 0, 1, 0},<br>+ {10, 0, 0, 0, 1, 0},<br>+ {8, 1, 0, 0, 1, 0},<br>+ {7, 5, 0, 0, 1, 0},<br>+ {6, 2, 0, 0, 1, 0}<br>+};<br>+<br>+const struct dll_setting default_ddr3_800_ctrl[2][7] = {<br>+ { /* 1N */<br>+ /* tap pi db(2) delay coarse */<br>+ {8, 2, 0, 0, 0, 0},<br>+ {8, 4, 0, 0, 0, 0},<br>+ {9, 5, 0, 0, 0, 0},<br>+ {6, 1, 0, 0, 0, 0},<br>+ {8, 4, 0, 0, 0, 0},<br>+ {10, 0, 0, 0, 0, 0},<br>+ {10, 0, 0, 0, 0, 0}, },<br>+ { /* 2N */<br>+ {2, 2, 1, 1, 0, 0},<br>+ {2, 4, 1, 1, 0, 0},<br>+ {3, 5, 0, 0, 0, 0},<br>+ {3, 2, 1, 1, 0, 0},<br>+ {2, 4, 1, 1, 0, 0},<br>+ {3, 6, 0, 0, 0, 0},<br>+ {3, 6, 0, 0, 0, 0}, }<br>+};<br>+<br>+const struct dll_setting default_ddr3_800_dqs[2][8] = {<br>+ { /* 1N */<br>+ {12, 0, 1, 0, 0, 0},<br>+ {1, 1, 1, 1, 1, 0},<br>+ {2, 4, 1, 1, 1, 0},<br>+ {3, 5, 0, 0, 1, 0},<br>+ {4, 3, 0, 0, 1, 0},<br>+ {5, 2, 0, 0, 1, 0},<br>+ {6, 1, 0, 0, 1, 0},<br>+ {6, 4, 0, 0, 1, 0}, },<br>+ { /* 2N */<br>+ {5, 6, 0, 0, 0, 0},<br>+ {8, 0, 0, 0, 0, 0},<br>+ {9, 4, 0, 0, 0, 0},<br>+ {10, 4, 1, 0, 0, 0},<br>+ {11, 3, 1, 0, 0, 0},<br>+ {12, 1, 1, 0, 0, 0},<br>+ {0, 1, 1, 1, 1, 0},<br>+ {0, 3, 1, 1, 1, 0}, }<br>+};<br>+<br>+const struct dll_setting default_ddr3_800_dq[2][8] = {<br>+ { /* 1N */<br>+ {4, 1, 0, 0, 1, 0},<br>+ {6, 4, 0, 0, 1, 0},<br>+ {8, 1, 0, 0, 1, 0},<br>+ {8, 6, 0, 0, 1, 0},<br>+ {9, 5, 0, 0, 1, 0},<br>+ {10, 2, 0, 0, 1, 0},<br>+ {10, 6, 1, 0, 1, 0},<br>+ {11, 4, 1, 0, 1, 0} },<br>+ { /* 2N */<br>+ {11, 0, 1, 0, 0, 0},<br>+ {0, 3, 1, 1, 1, 0},<br>+ {2, 1, 1, 1, 1, 0},<br>+ {2, 5, 1, 1, 1, 0},<br>+ {3, 5, 0, 0, 1, 0},<br>+ {4, 2, 0, 0, 1, 0},<br>+ {4, 6, 0, 0, 1, 0},<br>+ {5, 4, 0, 0, 1, 0}, }<br>+};<br>+<br>+const struct dll_setting default_ddr3_1067_ctrl[2][7] = {<br>+ { /* 1N */<br>+ {8, 5, 0, 0, 0, 0},<br>+ {7, 6, 0, 0, 0, 0},<br>+ {10, 2, 1, 0, 0, 0},<br>+ {0, 4, 4, 0, 0, 0},<br>+ {7, 6, 0, 0, 0, 0},<br>+ {9, 2, 1, 0, 0, 0},<br>+ {9, 2, 1, 0, 0, 0}, },<br>+ { /* 2N */<br>+ {1, 5, 1, 1, 0, 0},<br>+ {0, 6, 1, 1, 0, 0},<br>+ {3, 2, 0, 0, 0, 0},<br>+ {2, 6, 1, 1, 0, 0},<br>+ {0, 6, 1, 1, 0, 0},<br>+ {2, 2, 1, 1, 0, 0},<br>+ {2, 2, 1, 1, 0, 0}, }<br>+};<br>+<br>+const struct dll_setting default_ddr3_1067_dqs[2][8] = {<br>+ { /* 1N */<br>+ {2, 5, 1, 1, 1, 0},<br>+ {5, 1, 0, 0, 1, 0},<br>+ {6, 6, 0, 0, 1, 0},<br>+ {8, 0, 0, 0, 1, 0},<br>+ {8, 6, 0, 0, 1, 0},<br>+ {9, 6, 1, 0, 1, 0},<br>+ {10, 6, 1, 0, 1, 0},<br>+ {0, 1, 1, 1, 0, 0}, },<br>+ { /* 2N */<br>+ {6, 4, 0, 0, 0, 0},<br>+ {9, 1, 1, 0, 0, 0},<br>+ {10, 6, 1, 0, 0, 0},<br>+ {1, 0, 1, 1, 1, 0},<br>+ {1, 6, 1, 1, 1, 0},<br>+ {2, 5, 1, 1, 1, 0},<br>+ {3, 5, 0, 0, 1, 0},<br>+ {4, 1, 0, 0, 1, 0},<br>+ }<br>+};<br>+<br>+const struct dll_setting default_ddr3_1067_dq[2][8] = {<br>+ { /* 1N */<br>+ {6, 5, 0, 0, 1, 0},<br>+ {9, 3, 1, 0, 1, 0},<br>+ {0, 2, 1, 1, 0, 1},<br>+ {1, 0, 1, 1, 0, 1},<br>+ {2, 0, 1, 1, 0, 1},<br>+ {2, 5, 1, 1, 0, 1},<br>+ {3, 2, 0, 0, 0, 1},<br>+ {4, 1, 0, 0, 0, 1}, },<br>+ { /* 2N */<br>+ {10, 5, 1, 0, 0, 0},<br>+ {2, 3, 1, 1, 1, 0},<br>+ {4, 1, 0, 0, 1, 0},<br>+ {5, 0, 0, 0, 1, 0},<br>+ {6, 0, 0, 0, 1, 0},<br>+ {6, 5, 0, 0, 1, 0},<br>+ {7, 2, 0, 0, 1, 0},<br>+ {8, 1, 0, 0, 1, 0},<br>+ }<br>+};<br>+<br>+const struct dll_setting default_ddr3_1333_ctrl[2][7] = {<br>+ { /* 1N */<br>+ {8, 5, 0, 0, 0, 0},<br>+ {9, 0, 1, 0, 0, 0},<br>+ {10, 2, 1, 0, 0, 0},<br>+ {0, 0, 1, 1, 0, 0},<br>+ {9, 0, 1, 0, 0, 0},<br>+ {10, 4, 1, 0, 0, 0},<br>+ {10, 4, 1, 0, 0, 0}, },<br>+ { /* 2N */<br>+ {1, 6, 1, 1, 0, 0},<br>+ {2, 2, 1, 1, 0, 0},<br>+ {4, 2, 0, 0, 0, 0},<br>+ {3, 1, 1, 1, 0, 0},<br>+ {2, 2, 1, 1, 0, 0},<br>+ {4, 5, 0, 0, 0, 0},<br>+ {4, 5, 0, 0, 0, 0}, }<br>+};<br>+<br>+const struct dll_setting default_ddr3_1333_dqs[2][8] = {<br>+ { /* 1N */<br>+ {2, 4, 1, 1, 1, 0},<br>+ {5, 1, 0, 0, 1, 0},<br>+ {6, 6, 0, 0, 1, 0},<br>+ {8, 0, 0, 0, 1, 0},<br>+ {8, 6, 0, 0, 1, 0},<br>+ {9, 5, 1, 0, 1, 0},<br>+ {10, 6, 1, 0, 1, 0},<br>+ {0, 1, 1, 1, 0, 1}, },<br>+ { /* 2N */<br>+ {10, 4, 0, 0, 0, 0},<br>+ {0, 3, 1, 1, 1, 0},<br>+ {3, 2, 1, 1, 1, 0},<br>+ {5, 0, 0, 0, 1, 0},<br>+ {6, 1, 0, 0, 1, 0},<br>+ {7, 4, 0, 0, 1, 0},<br>+ {9, 2, 0, 0, 1, 0},<br>+ {9, 6, 0, 0, 1, 0}, }<br>+};<br>+<br>+const struct dll_setting default_ddr3_1333_dq[2][8] = {<br>+ { /* 1N */<br>+ {6, 5, 0, 0, 1, 0},<br>+ {9, 3, 1, 0, 1, 0},<br>+ {0, 2, 1, 1, 0, 1},<br>+ {1, 0, 1, 1, 0, 1},<br>+ {2, 0, 1, 1, 0, 1},<br>+ {2, 5, 1, 1, 0, 1},<br>+ {3, 2, 0, 0, 0, 1},<br>+ {4, 1, 0, 0, 0, 1}, },<br>+ { /* 2N */<br>+ {1, 3, 1, 1, 1, 0},<br>+ {5, 6, 0, 0, 1, 0},<br>+ {8, 5, 0, 0, 1, 0},<br>+ {10, 2, 0, 0, 1, 0},<br>+ {11, 1, 0, 0, 1, 0},<br>+ {12, 3, 1, 0, 1, 0},<br>+ {13, 6, 1, 0, 1, 0},<br>+ {0, 3, 1, 1, 0, 1}, }<br>+};<br>diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h<br>index 97c225b..0995435 100644<br>--- a/src/northbridge/intel/x4x/x4x.h<br>+++ b/src/northbridge/intel/x4x/x4x.h<br>@@ -250,6 +250,11 @@<br> u8 coarse;<br> };<br> <br>+struct rt_dqs_setting {<br>+ u8 tap;<br>+ u8 pi;<br>+};<br>+<br> enum n_banks {<br> N_BANKS_4 = 0,<br> N_BANKS_8 = 1,<br>@@ -305,6 +310,9 @@<br> struct dimminfo dimms[4];<br> u8 spd_map[4];<br> struct rcven_timings rcven_t[TOTAL_CHANNELS];<br>+ struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][RANKS_PER_CHANNEL][8];<br>+ struct dll_setting dqs_settings[TOTAL_CHANNELS][8];<br>+ struct dll_setting dq_settings[TOTAL_CHANNELS][8];<br> };<br> #define BOOT_PATH_NORMAL 0<br> #define BOOT_PATH_WARM_RESET 1<br>@@ -318,22 +326,6 @@<br> CTRL1,<br> CTRL2,<br> CTRL3,<br>- DQS1,<br>- DQS2,<br>- DQS3,<br>- DQS4,<br>- DQS5,<br>- DQS6,<br>- DQS7,<br>- DQS8,<br>- DQ1,<br>- DQ2,<br>- DQ3,<br>- DQ4,<br>- DQ5,<br>- DQ6,<br>- DQ7,<br>- DQ8<br> };<br> <br> #ifndef __BOOTBLOCK__<br>@@ -348,6 +340,22 @@<br> u32 fsb2mhz(u32 speed);<br> u32 ddr2mhz(u32 speed);<br> <br>+extern const struct dll_setting default_ddr2_667_ctrl[7];<br>+extern const struct dll_setting default_ddr2_800_ctrl[7];<br>+extern const struct dll_setting default_ddr3_800_ctrl[2][7];<br>+extern const struct dll_setting default_ddr3_1067_ctrl[2][7];<br>+extern const struct dll_setting default_ddr3_1333_ctrl[2][7];<br>+extern const struct dll_setting default_ddr2_667_dqs[8];<br>+extern const struct dll_setting default_ddr2_800_dqs[8];<br>+extern const struct dll_setting default_ddr3_800_dqs[2][8];<br>+extern const struct dll_setting default_ddr3_1067_dqs[2][8];<br>+extern const struct dll_setting default_ddr3_1333_dqs[2][8];<br>+extern const struct dll_setting default_ddr2_667_dq[8];<br>+extern const struct dll_setting default_ddr2_800_dq[8];<br>+extern const struct dll_setting default_ddr3_800_dq[2][8];<br>+extern const struct dll_setting default_ddr3_1067_dq[2][8];<br>+extern const struct dll_setting default_ddr3_1333_dq[2][8];<br>+<br> struct acpi_rsdp;<br> #ifndef __SIMPLE_DEVICE__<br> unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);<br></pre><p>To view, visit <a href="https://review.coreboot.org/22327">change 22327</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22327"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934 </div>
<div style="display:none"> Gerrit-Change-Number: 22327 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>