<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22288">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/amd/stoneyridge: Replace AMD types with coreboot types.<br><br>AMD uses u8, u16 and u32 types, while coreboot comunity uses uint8_t,<br>uint16_t and uint32_t. Replace the types in southbridge.h function<br>prototypes and the actual functions declared by these prototypes.<br><br>BUG=b:68007655<br><br>Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/early_setup.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/sb_util.c<br>3 files changed, 39 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22288/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c<br>index ecae7ab..fc61c6b 100644<br>--- a/src/soc/amd/stoneyridge/early_setup.c<br>+++ b/src/soc/amd/stoneyridge/early_setup.c<br>@@ -33,7 +33,7 @@<br> <br> void configure_stoneyridge_uart(void)<br> {<br>- u8 byte, byte2;<br>+ uint8_t byte, byte2;<br> <br> if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)<br> return;<br>@@ -71,7 +71,7 @@<br> <br> void sb_pci_port80(void)<br> {<br>- u8 byte;<br>+ uint8_t byte;<br> pci_devfn_t dev;<br> <br> dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>@@ -83,7 +83,7 @@<br> <br> void sb_lpc_port80(void)<br> {<br>- u8 byte;<br>+ uint8_t byte;<br> pci_devfn_t dev;<br> <br> /* Enable LPC controller */<br>@@ -103,7 +103,7 @@<br> void sb_lpc_decode(void)<br> {<br> pci_devfn_t dev;<br>- u32 tmp = 0;<br>+ uint32_t tmp = 0;<br> <br> /* Enable I/O decode to LPC bus */<br> dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>@@ -170,7 +170,7 @@<br> static void lpc_wideio_window(uint16_t base, uint16_t size)<br> {<br> pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>- u32 tmp;<br>+ uint32_t tmp;<br> <br> /* Support 512 or 16 bytes per range */<br> assert(size == 512 || size == 16);<br>@@ -210,7 +210,7 @@<br> lpc_wideio_window(base, 16);<br> }<br> <br>-int s3_save_nvram_early(u32 dword, int size, int nvram_pos)<br>+int s3_save_nvram_early(uint32_t dword, int size, int nvram_pos)<br> {<br> int i;<br> printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n",<br>@@ -225,9 +225,9 @@<br> return nvram_pos;<br> }<br> <br>-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)<br>+int s3_load_nvram_early(int size, uint32_t *old_dword, int nvram_pos)<br> {<br>- u32 data = *old_dword;<br>+ uint32_t data = *old_dword;<br> int i;<br> for (i = 0; i < size; i++) {<br> outb(nvram_pos, BIOSRAM_INDEX);<br>@@ -243,7 +243,7 @@<br> <br> void sb_clk_output_48Mhz(void)<br> {<br>- u32 ctrl;<br>+ uint32_t ctrl;<br> <br> /*<br> * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so<br>@@ -260,7 +260,7 @@<br> {<br> /* Make sure the base address is predictable */<br> device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>- u32 base, enables;<br>+ uint32_t base, enables;<br> <br> base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);<br> enables = base & 0xf;<br>@@ -275,7 +275,7 @@<br> return (uintptr_t)base;<br> }<br> <br>-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)<br>+void sb_set_spi100(uint16_t norm, uint16_t fast, uint16_t alt, uint16_t tpm)<br> {<br> uintptr_t base = sb_spibase();<br> write16((void *)base + SPI100_SPEED_CONFIG,<br>@@ -294,7 +294,7 @@<br> & ~SPI_RD4DW_EN_HOST);<br> }<br> <br>-void sb_set_readspeed(u16 norm, u16 fast)<br>+void sb_set_readspeed(uint16_t norm, uint16_t fast)<br> {<br> uintptr_t base = sb_spibase();<br> write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1)<br>@@ -303,7 +303,7 @@<br> | (fast << SPI_FAST_SPEED_SH));<br> }<br> <br>-void sb_read_mode(u32 mode)<br>+void sb_read_mode(uint32_t mode)<br> {<br> uintptr_t base = sb_spibase();<br> write32((void *)base + SPI_CNTRL0,<br>@@ -315,7 +315,7 @@<br> {<br> device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */<br> <br>- u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);<br>+ uint32_t spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);<br> pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase<br> | ROUTE_TPM_2_SPI);<br> }<br>@@ -331,7 +331,7 @@<br> */<br> void sb_enable_rom(void)<br> {<br>- u8 reg8;<br>+ uint8_t reg8;<br> pci_devfn_t dev;<br> <br> dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 55ded9f..5302bc0 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -1,7 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2010 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2010-2017 Advanced Micro Devices, Inc.<br> * Copyright (C) 2014 Sage Electronic Engineering, LLC<br> *<br> * This program is free software; you can redistribute it and/or modify<br>@@ -264,28 +264,28 @@<br> void sb_lpc_port80(void);<br> void sb_lpc_decode(void);<br> void sb_pci_port80(void);<br>-void sb_read_mode(u32 mode);<br>-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);<br>-void sb_set_readspeed(u16 norm, u16 fast);<br>+void sb_read_mode(uint32_t mode);<br>+void sb_set_spi100(uint16_t norm, uint16_t fast, uint16_t alt, uint16_t tpm);<br>+void sb_set_readspeed(uint16_t norm, uint16_t fast);<br> void sb_tpm_decode_spi(void);<br> void lpc_wideio_512_window(uint16_t base);<br> void lpc_wideio_16_window(uint16_t base);<br>-u8 pm_read8(u8 reg);<br>-u16 pm_read16(u8 reg);<br>-u32 pm_read32(u8 reg);<br>-void pm_write8(u8 reg, u8 value);<br>-void pm_write16(u8 reg, u16 value);<br>-void pm_write32(u8 reg, u32 value);<br>-u8 smi_read8(u8 reg);<br>-u16 smi_read16(u8 reg);<br>-u32 smi_read32(u8 reg);<br>-void smi_write8(u8 reg, u8 value);<br>-void smi_write16(u8 reg, u16 value);<br>-void smi_write32(u8 reg, u32 value);<br>+uint8_t pm_read8(uint8_t reg);<br>+uint16_t pm_read16(uint8_t reg);<br>+uint32_t pm_read32(uint8_t reg);<br>+void pm_write8(uint8_t reg, uint8_t value);<br>+void pm_write16(uint8_t reg, uint16_t value);<br>+void pm_write32(uint8_t reg, uint32_t value);<br>+uint8_t smi_read8(uint8_t reg);<br>+uint16_t smi_read16(uint8_t reg);<br>+uint32_t smi_read32(uint8_t reg);<br>+void smi_write8(uint8_t reg, uint8_t value);<br>+void smi_write16(uint8_t reg, uint16_t value);<br>+void smi_write32(uint8_t reg, uint32_t value);<br> uint16_t pm_acpi_pm_cnt_blk(void);<br>-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);<br>+int s3_load_nvram_early(int size, uint32_t *old_dword, int nvram_pos);<br> void s3_resume_init_data(void *FchParams);<br>-int s3_save_nvram_early(u32 dword, int size, int nvram_pos);<br>+int s3_save_nvram_early(uint32_t dword, int size, int nvram_pos);<br> void bootblock_fch_early_init(void);<br> <br> #endif /* __STONEYRIDGE_H__ */<br>diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c<br>index ebf791d..707e9bd 100644<br>--- a/src/soc/amd/stoneyridge/sb_util.c<br>+++ b/src/soc/amd/stoneyridge/sb_util.c<br>@@ -15,32 +15,32 @@<br> <br> #include <soc/southbridge.h><br> <br>-void pm_write8(u8 reg, u8 value)<br>+void pm_write8(uint8_t reg, uint8_t value)<br> {<br> write8((void *)(PM_MMIO_BASE + reg), value);<br> }<br> <br>-u8 pm_read8(u8 reg)<br>+uint8_t pm_read8(uint8_t reg)<br> {<br> return read8((void *)(PM_MMIO_BASE + reg));<br> }<br> <br>-void pm_write16(u8 reg, u16 value)<br>+void pm_write16(uint8_t reg, uint16_t value)<br> {<br> write16((void *)(PM_MMIO_BASE + reg), value);<br> }<br> <br>-u16 pm_read16(u8 reg)<br>+uint16_t pm_read16(uint8_t reg)<br> {<br> return read16((void *)(PM_MMIO_BASE + reg));<br> }<br> <br>-void pm_write32(u8 reg, u32 value)<br>+void pm_write32(uint8_t reg, uint32_t value)<br> {<br> write32((void *)(PM_MMIO_BASE + reg), value);<br> }<br> <br>-u32 pm_read32(u8 reg)<br>+uint32_t pm_read32(uint8_t reg)<br> {<br> return read32((void *)(PM_MMIO_BASE + reg));<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22288">change 22288</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22288"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e </div>
<div style="display:none"> Gerrit-Change-Number: 22288 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>