<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22269">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/reks: override USB2 Phy settings on BSW D-Stepping SOC<br><br>Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...<br><br>Base on Intel recommendation, override following<br>settings for USB2 port 1/2/3 on BSW D-stepping SOC.<br><br>1. Set USB[1] register for right side to 7321<br>2. Set USB[2] register for left side to 7021<br>3. Set USB[3] register for CCD to 7021<br><br>Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273<br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br>Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com><br><br>Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/cyan/variants/reks/Makefile.inc<br>A src/mainboard/google/cyan/variants/reks/ramstage.c<br>2 files changed, 41 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22269/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc<br>index 6577124..86499b4 100644<br>--- a/src/mainboard/google/cyan/variants/reks/Makefile.inc<br>+++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc<br>@@ -17,6 +17,7 @@<br> romstage-y += spd_util.c<br> <br> ramstage-y += gpio.c<br>+ramstage-y += ramstage.c<br> <br> SPD_BIN = $(obj)/spd.bin<br> <br>diff --git a/src/mainboard/google/cyan/variants/reks/ramstage.c b/src/mainboard/google/cyan/variants/reks/ramstage.c<br>new file mode 100644<br>index 0000000..27f9dfa<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/reks/ramstage.c<br>@@ -0,0 +1,40 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/ramstage.h><br>+<br>+void board_silicon_USB2_override(SILICON_INIT_UPD *params)<br>+{<br>+    if (SocStepping() >= SocD0) {<br>+             //D-Stepping<br>+         //USB2[1] right external port<br>+                params->Usb2Port1PerPortPeTxiSet = 7;<br>+             params->Usb2Port1PerPortTxiSet = 3;<br>+               params->Usb2Port1IUsbTxEmphasisEn = 2;<br>+            params->Usb2Port1PerPortTxPeHalf = 1;<br>+<br>+          //USB2[2] left external port<br>+         params->Usb2Port2PerPortPeTxiSet = 7;<br>+             params->Usb2Port2PerPortTxiSet = 0;<br>+               params->Usb2Port2IUsbTxEmphasisEn = 2;<br>+            params->Usb2Port2PerPortTxPeHalf = 1;<br>+<br>+          //USB2[3] CCD<br>+                params->Usb2Port3PerPortPeTxiSet = 7;<br>+             params->Usb2Port3PerPortTxiSet = 0;<br>+               params->Usb2Port3IUsbTxEmphasisEn = 2;<br>+            params->Usb2Port3PerPortTxPeHalf = 1;<br>+     }<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22269">change 22269</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22269"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 </div>
<div style="display:none"> Gerrit-Change-Number: 22269 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>